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參數(shù)資料
| 型號(hào)： | HPC-DEV-SYS2 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance Communications MicroController |
| 中文描述： | 高性能通信微控制器 |
| 文件頁數(shù)： | 18/30頁 |
| 文件大?。?/td> | 362K |
| 代理商： | HPC-DEV-SYS2 |
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HDLC Functional Description
(Continued)
TL/DD/10422–31
FIGURE 17. 64 kbit/56 kbit Rate Adaption Timing Diagram
dressing handling and CRC checking. All data between the
flags is shifted through two 8-bit serial shift registers before
being loaded into the buffer register. The user programma-
ble address register values are compared to the incoming
data while it resides in the shift registers. If an address
match occurs or if operating in the transparent address rec-
ognition mode, the DMA channel is signaled that attention is
required and the data is transferred by it to external memo-
ry. Appropriate interrupts are generated to the CPU on the
reception of a complete frame, or on the occurance of a
frame error.
The receive interrupt, in conjunction with status data in the
control registers allows interrupts to be generated on the
following conditionsDframe length error, CRC error, receive
error, abort and receive complete.
To support V.120 UI data packets at the ‘‘R’’ interface, pro-
prietary CRC algorithms, and test equipment the two bytes
preceding the closing flag (usually the CRC bytes) will be
loaded into registers. The two bytes can then be read by the
CPU and placed into memory. The DMA address pointers
used for that particular message will already contain the
address that the first byte should be placed into.
RECEIVER FEATURES
Flag sharing: the closing flag of one packet may be shared
as the opening flag of the next. Receiver will also be able to
share a zero between flagsD011111101111110 is a valid
two flag sequence for receive (not transmit).
Interframe fill: the receiver automatically accepts either re-
peated flags, repeated aborts, or all ‘1’s as the interframe
fill.
Idle: Reception of successive flags as the interframe fill se-
quence to be signaled to the user by setting the Flag bit in
the Receiver Status register.
Short Frame Rejection: Reception of greater than 2 bytes
but less than 4 bytes between flags will generate a frame
error, terminating reception of the current frame and setting
the Frame Error (FER) status bit in the Receive Control and
Status register. Reception of less than 2 bytes will be ig-
nored.
Abort: the 7 ‘1’s abort sequence will be immediately recog-
nized and will cause the receiver to reinitialize and return to
searching the incoming data for an opening flag. Reception
of the abort will cause the abort status bit in the Interrupt
Error Status register to be set and will signal an End of
Message (EOMR).
Bit/Byte boundaries: The message length between packet
headers may have any number of bits and it is not confined
to an integral number of bytes. Three bits in the status regis-
ter are used to indicate the number of valid bits in the last
byte.
Address Recognition: Two user programmable bytes are
available to allow frame address recognition on the two
bytes immediately following the opening flag. When the re-
ceived address matches the programmed value(s), the
frame is passed through to the DMA channel. If no match
occurs, the received frame address information is disregard-
ed and the receiver returns to searching for the next open-
ing flag and the address recognition process starts anew.
Support is provided to allow recognition of the Broadcast
address. Additionally, a transparent mode of operation is
available where no address decoding is done.
HDLC INTERRUPT CONDITIONS
The end of message interrupt (EOM) indicates that a com-
plete frame has been received or transmitted by the HDLC
controller. Thus, there are four separate sources for this
interrupt, two each from each HDLC channel. The Message
Control Register contains the pending bits for each source.
HDLC ERROR DETECTION
The HDLC/DMA detects several error conditions and re-
ports them in the two Error Status Registers. These condi-
tions are a DMA transmitter underrun, a DMA receiver over-
run, a CRC error, a frame too long, a frame too short, and an
aborted message.
HDLC CHANNEL CLOCK
Each HDLC channel uses the falling edge of the clock to
sample the receive data. Outgoing transmit data is shifted
out on the rising edge of the external clock. The maximum
data rate when using the externally provided clocks is
4.65 Mb/s.
The receiver/transmitter pair can share a single clock input
to save I/O pins, or the inputs can be separated to allow
different receive and transmit clocks. This feature allows the
receiver and transmitter to operate at different frequencies
or enables them to each be synchronized to different parts
of the user’s system.
CYCLIC REDUNDACY CHECK
There are two standard CRC codes used in generating the
16-bit Frame Check Sequence (FCS) that is appended to
the end of the data frame. Both codes are supported and
18
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