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參數(shù)資料
| 型號(hào)： | HPC467064EL20 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | High-Performance microController with a 16k UV Erasable CMOS EPROM |
| 中文描述： | UVPROM, MICROCONTROLLER, CQCC68 |
| 封裝： | WINDOWED, LDCC-68 |
| 文件頁數(shù)： | 12/34頁 |
| 文件大?。?/td> | 415K |
| 代理商： | HPC467064EL20 |
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Pin Descriptions
The HPC167064 is available only in 68-pin LDCC package.
I/O PORTS
Port A is a 16-bit bidirectional I/O port with a data direction
register to enable each separate pin to be individually de-
fined as an input or output. When accessing external memo-
ry, port A is used as the multiplexed address/data bus.
Port B is a 16-bit port with 12 bits of bidirectional I/O similar
in structure to Port A. Pins B10, B11, B12 and B15 are gen-
eral purpose outputs only in this mode. Port B may also be
configured via a 16-bit function register BFUN to individually
allow each pin to have an alternate function.
B0:
B1:
B2:
B3:
B4:
B5:
B6:
B7:
B8:
B9:
B10: UA0
B11: WRRDY Write Ready Output for UPI Mode
B12:
B13: TS2
Timer Synchronous Output
B14: TS3
Timer Synchronous Output
B15: RDRDY Read Ready Output for UPI Mode
TDX
UART Data Output
CKX
T2IO
T3IO
SO
SK
HLDA
TS0
TS1
UART Clock (Input or Output)
Timer2 I/O Pin
Timer3 I/O Pin
MICROWIRE/PLUS Output
MICROWIRE/PLUS Clock (Input or Output)
Hold Acknowledge Output
Timer Synchronous Output
Timer Synchronous Output
Address 0 Input for UPI Mode
When accessing external memory, four bits of port B are
used as follows:
B10: ALE
B11: WR
B12: HBE
Address Latch Enable Output
Write Output
High Byte Enable Output/Input
(sampled at reset)
Read Output
B15: RD
Port I is an 8-bit input port that can be read as general
purpose inputs and is also used for the following functions:
I0:
I1:
I2:
I3:
I4:
I5:
I6:
I7:
NMI
INT2
INT3
INT4
SI
RDX
Nonmaskable Interrupt Input
Maskable Interrupt/Input Capture/URD
Maskable Interrupt/Input Capture/UWR
Maskable Interrupt/Input Capture
MICROWIRE/PLUS Data Input
UART Data Input
Port D is an 8-bit input port that can be used as general
purpose digital inputs.
Port P is a 4-bit output port that can be used as general
purpose data, or selected to be controlled by timers 4
through 7 in order to generate frequency, duty cycle and
pulse width modulated outputs.
POWER SUPPLY PINS
V
CC1
and
V
CC2
GND
Positive Power Supply
Ground for On-Chip Logic
DGND
Ground for Output Buffers
Note:
There are two electrically connected V
CC
pins on the chip, GND and
DGND are electrically isolated. Both V
CC
pins and both ground pins
must be used.
CLOCK PINS
CKI
The Chip System Clock Input
CKO
The Chip System Clock Output (inversion of CKI)
Pins CKI and CKO are usually connected across an external
crystal.
CK2
Clock Output (CKI divided by 2)
OTHER PINS
WO
This is an active low open drain output that sig-
nals an illegal situation has been detected by the
WATCHDOG logic.
ST1
Bus Cycle Status Output: indicates first opcode
fetch.
ST2
Bus Cycle Status Output: indicates machine
states (skip, interrupt and first instruction cycle).
RESET
is an active low input that forces the chip to re-
start and sets the ports in a TRI-STATE mode.
RDY/HLD has two uses, selected by a software bit. It’s ei-
ther an input to extend the bus cycle for slower
memories, or a HOLD request input to put the
bus in a high impedance state for DMA purpos-
es.
NC
(no connection) do not connect anything to this
pin.
EXM
Has two uses. External memory enable (active
high) which disables internal EPROM and maps
it to external memory, and is V
PP
during EPROM
mode.
EI
External
interrupt
FFF1:FFF0. (Rising/falling edge or high/low lev-
el sensitive). Alternately can be configured as
4th input capture.
EXUI
External interrupt which is internally OR’ed with
the
UART
interrupt
FFF3:FFF2 (Active Low).
with
vector
address
with
vector
address
12
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