參數(shù)資料
型號： HPC467064EL20
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： High-Performance microController with a 16k UV Erasable CMOS EPROM
中文描述： UVPROM, MICROCONTROLLER, CQCC68
封裝： WINDOWED, LDCC-68
文件頁數(shù)： 5/34頁
文件大小： 415K
代理商： HPC467064EL20
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figures 1 thru 5 ). V
CC
e
5V
g
10%, T
A
e
0
§
C to
a
70
§
C for HPC467064.
Symbol and Formula
Parameter
Min
Max
Units
Notes
f
C
t
C1
e
1/f
C
t
CKIH
t
CKIL
t
C
e
2/f
C
t
WAIT
e
t
C
t
DC1C2R
t
DC1C2F
f
U
e
f
C
/8
f
MW
f
XIN
e
f
C
/22
t
XIN
e
t
C
CKI Operating Frequency
CKI Clock Period
CKI High Time
CKI Low Time
CPU Timing Cycle
CPU Wait State Period
Delay of CK2 Rising Edge after CKI Falling Edge
Delay of CK2 Falling Edge after CKI Falling Edge
2
30
500
MHz
ns
ns
ns
ns
ns
ns
ns
33
22.5
22.5
66
66
0
0
55
55
(Note 2)
(Note 2)
External UART Clock Input Frequency
External MICROWIRE/PLUS Clock Input Frequency
3.75
**
1.875
MHz
MHz
External Timer Input Frequency
Pulse Width for Timer Inputs
1.364
MHz
ns
66
t
UWS
MICROWIRE Setup TimeDMaster
MICROWIRE Setup TimeDSlave
100
20
ns
t
UWH
MICROWIRE Hold TimeDMaster
MICROWIRE Hold TimeDSlave
20
50
ns
t
UWV
MICROWIRE Output Valid TimeDMaster
MICROWIRE Output Valid TimeDSlave
50
150
ns
t
SALE
e
*/4
t
C
a
40
t
HWP
e
t
C
a
10
t
HAE
e
t
C
a
85
t
HAD
e
*/4
t
C
a
85
t
BF
e
(/2
t
C
a
66
t
BE
e
(/2
t
C
a
66
HLD Falling Edge before ALE Rising Edge
HLD Pulse Width
HLDA Falling Edge after HLD Falling Edge
HLDA Rising Edge after HLD Rising Edge
Bus Float after HLDA Falling Edge
Bus Enable after HLDA Rising Edge
90
76
ns
ns
ns
ns
ns
ns
151
135
99
(Note 3)
(Note 5)
(Note 5)
99
t
UAS
t
UAH
t
RPW
t
OE
t
OD
t
DRDY
t
WDW
t
UDS
t
UDH
t
A
Address Setup Time to Falling Edge of URD
Address Hold Time from Rising Edge of URD
URD Pulse Width
URD Falling Edge to Output Data Valid
Rising Edge of URD to Output Data Invalid
RDRDY Delay from Rising Edge of URD
UWR Pulse Width
Input Data Valid before Rising Edge of UWR
Input Data Hold after Rising Edge of UWR
WRRDY Delay from Rising Edge of UWR
10
10
100
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
45
70
(Note 6)
40
10
20
70
t
DC1ALER
t
DC1ALEF
t
DC2ALER
e
(/4
t
C
a
20
t
DC2ALEF
e
(/4
t
C
a
20
t
LL
e
(/2
t
C
b
9
t
ST
e
(/4
t
C
b
7
t
VP
e
(/4
t
C
b
5
Delay from CKI Rising Edge to ALE Rising Edge
Delay from CKI Rising Edge to ALE Falling Edge
Delay from CK2 Rising Edge to ALE Rising Edge
Delay from CK2 Falling Edge to ALE Falling Edge
ALE Pulse Width
Setup of Address Valid before ALE Falling Edge
Hold of Address Valid after ALE Falling Edge
0
0
35
35
37
37
ns
ns
ns
ns
ns
ns
ns
(Notes 1, 2)
(Notes 1, 2)
24
9
11
C
T
M
E
U
A
5
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