參數(shù)資料
型號(hào)： HPC
文件頁(yè)數(shù)： 1/30頁(yè)
文件大?。?/td> 361K
代理商： HPC
TL/U/9982
H
PRELIMINARY
November 1988
HPCCOREA High-Performance Microcontroller Core
General Description
The HPCCOREA Megacell is the ASIC HPC
TM
Core Mega-
cell available in the cell based design library. The HPC core
is the basis for the HPC family of High Performance micro-
controllers available as standard products from National
Semiconductor. Each member of the family is built around
this core CPU with a unique memory and I/O configuration
to suit specific applications. Therefore, designers can now
customize the peripherals surrounding the HPC core to
meet their precise needs, while integrating additional sys-
tem logic onto the same die. A single chip system solution
becomes possible. All Cell Based IC’s are fabricated in Na-
tional’s advanced 2
m
dual layer metal microCMOS technol-
ogy. This process combined with an advanced architecture
offers fast, flexible I/O control, efficient data manipulation
and high speed computation.
The HPC core Megacell permits a complete microcomputer
environment and more on a single chip. Customization of
microcontroller applications and inclusion of surrounding
system logic and memory, produce a cost effective system
solution for high performance applications. Core functions
such as 4 16-bit timers with 3 input capture registers, vec-
tored interrupts, WATCHDOG
TM
logic, and MICROWIRE/
PLUS
TM
provide efficient paths for system integration. The
ability to address up to 64 kbytes of memory enables the
HPC core to be used in powerful applications typically per-
formed by microprocessors and expensive peripheral chips.
The microCMOS process results in very low current drain
and enables the user to select the optimum speed/power
product for his system. The IDLE and HALT modes provide
further current savings.
HPC Core Features
Y
16-bit architecture, both byte and word
Y
16-bit data bus, ALU and registers
Y
64 kbytes of memory mapped addressing
Y
FASTD240 ns for register instructions when using
17.0 MHz clock
Y
High code efficiencyDmost instructions are single byte
Y
16 x 16 multiply and 32 x 16 divide
Y
Eight vectored interrupt sources
Y
Four 16-bit timer/counters
Y
Three 16-bit capture registers
Y
WATCHDOG logic
Y
MICROWIRE/PLUS serial I/O interface
Y
CMOSDvery low power save modes: IDLE and HALT
Y
Programmable wait states
Y
16-bit general purpose/address data bus I/O port
Y
8-bit general purpose input port
Y
256 byte RAM
Y
Megacell Test Logic
Y
Enhanced access to core features
Block Diagram
DHPC Core Megacell
TL/U/9982–1
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
HPC
TM
, MICROWIRE
TM
, MICROWIRE/PLUS
TM
, MOLE
TM
and WATCHDOG
TM
are trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
RRD-B30M115/Printed in U. S. A.
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