參數(shù)資料
型號： HPC467064EL20
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： High-Performance microController with a 16k UV Erasable CMOS EPROM
中文描述： UVPROM, MICROCONTROLLER, CQCC68
封裝： WINDOWED, LDCC-68
文件頁數(shù)： 3/34頁
文件大小： 415K
代理商： HPC467064EL20
20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 andFigures 1 thru5 ). V
CC
e
5V
g
5%
*
, T
A
e b
55
§
C to
a
125
§
C for HPC167064 and V
CC
e
5V
g
10%,
T
A
e
0
§
C to
a
70
§
C for HPC467064
Symbol and Formula
Parameter
Min
Max
Units
Notes
f
C
t
C1
e
1/f
C
t
CKIH
t
CKIL
t
C
e
2/f
C
t
WAIT
e
t
C
t
DC1C2R
t
DC1C2F
f
U
e
f
C
/8
f
MW
f
XIN
e
f
C
/22
t
XIN
e
t
C
CKI Operating Frequency
CKI Clock Period
CKI High Time
CKI Low Time
CPU Timing Cycle
CPU Wait State Period
Delay of CK2 Rising Edge after CKI Falling Edge
Delay of CK2 Falling Edge after CKI Falling Edge
2
20
500
MHz
ns
ns
ns
ns
ns
ns
ns
50
22.5
22.5
100
100
0
0
55
55
(Note 2)
(Note 2)
External UART Clock Input Frequency
External MICROWIRE/PLUS Clock Input Frequency
2.5
**
1.25
MHz
MHz
External Timer Input Frequency
Pulse Width for Timer Inputs
0.91
MHz
ns
100
t
UWS
MICROWIRE Setup TimeDMaster
MICROWIRE Setup TimeDSlave
100
20
ns
t
UWH
MICROWIRE Hold TimeDMaster
MICROWIRE Hold TimeDSlave
20
50
ns
t
UWV
MICROWIRE Output Valid TimeDMaster
MICROWIRE Output Valid TimeDSlave
50
150
ns
t
SALE
e
*/4
t
C
a
40
t
HWP
e
t
C
a
10
t
HAE
e
t
C
a
100
t
HAD
e
*/4
t
C
a
85
t
BF
e
(/2
t
C
a
66
t
BE
e
(/2
t
C
a
66
HLD Falling Edge before ALE Rising Edge
HLD Pulse Width
HLDA Falling Edge after HLD Falling Edge
HLDA Rising Edge after HLD Rising Edge
Bus Float after HLDA Falling Edge
Bus Enable after HLDA Rising Edge
115
110
ns
ns
ns
ns
ns
ns
200
160
116
(Note 3)
(Note 5)
(Note 5)
116
t
UAS
t
UAH
t
RPW
t
OE
t
OD
t
DRDY
t
WDW
t
UDS
t
UDH
(HPC467064)
t
UDH
(HPC167064)
t
A
Address Setup Time to Falling Edge of URD
Address Hold Time from Rising Edge of URD
URD Pulse Width
URD Falling Edge to Output Data Valid
Rising Edge of URD to Output Data Invalid
RDRDY Delay from Rising Edge of URD
UWR Pulse Width
Input Data Valid before Rising Edge of UWR
Input Data Hold after Rising Edge of UWR
10
10
100
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
60
45
70
(Note 6)
40
10
20
25
*
WRRDY Delay from Rising Edge of UWR
70
C
T
M
E
U
*
See NORMAL RUNNING MODE.
**
This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
Note:
C
L
e
40 pF.
Note 1:
These AC Characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
CKIR
and t
CKIL
) on CKI input less than 2.5 ns.
Note 2:
Do not design with this parameter unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either CKI
or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3:
t
HAE
is spec’d for case with HLD falling edge occurring at the latest time can be accepted during the present CPU cycle being executed. If HLD falling edge
occurs later, t
HAE
may be as long as (3t
C
a
4 WS
a
72t
C
a
100) depending on the following CPU instruction cycles, its wait states and ready input.
Note 4:
WS
e
t
WAIT
c
(number of pre-programmed wait states). Minimum and maximum values are calculated at maximum operating frequency, t
c
e
20.00 MHz,
with one wait state programmed.
Note 5:
Due to emulation restrictionsDactual limits will be better.
Note 6:
Due to tester limitationsDactual limits will be better.
3
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