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參數(shù)資料
| 型號： | HS1-82C37ARH-Sample |
| 廠商： | Harris Corporation |
| 英文描述： | Radiation Hardened CMOS High Performance Programmable DMA Controller |
| 中文描述： | 輻射加固的CMOS高性能可編程DMA控制器 |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 253K |
| 代理商： | HS1-82C37ARH-SAMPLE |
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HS-82C37ARH
Application Information
Figure 12 shows an application for a DMA system utilizing
the HS-82C37ARH DMA controller and the HS-80C86RH
Microprocessor. In this application, the HS-82C37ARH DMA
controller is used to improve system performance by allow-
ing an I/O device to transfer data directly to or from system
memory.
Components
The system clock is generated by the HS-82C85RH clock
controllers generator and is inverted to meet the clock high
and low times required by the HS-82C37ARH DMA control-
ler. The four OR gates are used to support the HS-80C86RH
Microprocessor in minimum mode by producing the control
signals used by the processor to access memory or I/O. A
decoder is used to generate chip select for the DMA control-
ler and memory. The HS-82C37ARH multiplexes the most
significant bits of the address on its data outputs (DB0 - 7),
so the 82C82 octal latch is used to demultiplex the address.
A three-state inverter is used to generate the BHE signal
using the A0 output of the HS-82C37ARH. Hold Acknowl-
edge (HLDA) and Address Enable (AEN) are “ORed”
together and used to deactivate the microprocessors 82C82
transceiver to insure that the DMA controller does not have
bus contention with the microprocessor.
Operation
A DMA request (DREQ) is generated by the I/O device. After
receiving the DMA request, the DMA controller will issue a
Hold Request (HRQ) to the processor. The system busses
are not released to the DMA controller until a Hold Acknowl-
edge (HLDA) signal is returned to the DMA controller from
the HS-80C86RH processor. After the Hold Acknowledge
has been received, addresses and control signals are gener-
ated by the DMA controller to accomplish the DMA transfers.
Data is transferred directly from the I/O device to memory (or
vice versa) with IOR and MEMW (or MEMR and IOW) being
active. Note that data is not read into or driven out of the
DMA controller in I/O-to-Memory or Memory-to-I/O data
transfers.
FIGURE 12. APPLICATION FOR DMA SYSTEM
STB
OE
82C82
CLK
CS
ADSTB
AEN
A0-7
DB0-7
EOP
IOW
MEMR
MEMW
HRQ
DREQ0
DACK0
IOR
HLDA
DECODER
MEMCS
CLK
HS-82C85RH
HLDA
HLDA
HRQ
ALE
AD0
AD15
VDD
MN/MX
M/10
RD
WR
BHE
MEMW
IOR
IOW
MEMR
MEMR
MEMW
MEMCS
MEMORY
HS-80C86RH
DATA BUS
ADDRESS BUS
DATA BUS
STB
OE
82C82
ADDRESS
BUS
BHE
A0
VDD
CS
DREQ
I/O
DEVICE
IOR
IOW
HS-82C37ARH
Spec Number
518058
相關PDF資料 |
PDF描述 |
|---|---|
| HS1-82C37ARH-Q | Radiation Hardened CMOS High Performance Programmable DMA Controller |
| HS-82C37 | Radiation Hardened CMOS High Performance Programmable DMA Controller |
| HS1-82C37ARH-8 | Radiation Hardened CMOS High Performance Programmable DMA Controller |
| HS9-82C37ARH-8 | Radiation Hardened CMOS High Performance Programmable DMA Controller |
| HS1-82C37ARH-Q | Radiation Hardened CMOS High Performance Programmable DMA Controller |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HS1-82C52RH-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UART |
| HS1-82C54RH | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Radiation Hardened CMOS Programmable Interval Timer |
| HS1-82C54RH/PROTO | 制造商:Intersil Corporation 功能描述:RAD HARD CMOS PROGRAMMABLE INTERVAL TIMER,PROTO,CLASS V - Rail/Tube |
| HS1-82C54RH-8 | 制造商:Intersil Corporation 功能描述:PROGRAMMABLE TIMER SGL 24PIN SBDIP - Rail/Tube |
| HS1-82C54RH-Q | 制造商:Intersil Corporation 功能描述:PROGRAMMABLE TIMER SGL 24PIN SBCDIP - Rail/Tube |
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