參數(shù)資料
型號(hào)： HV7131E1
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： CMOS IMAGE SENSOR With 8-bit ADC
中文描述： SPECIALTY ANALOG CIRCUIT, CQCC48
封裝： CERAMIC, LCC-48
文件頁(yè)數(shù)： 51/61頁(yè)
文件大?。?/td> 2621K
代理商： HV7131E1
HV7131GP
2004/10/29 V2.4 51
Data Output Timing and Interface
Y [7 :0 ]
V C L K
C [7 :0 ]
H S Y N C
X
Y 0
Y 1
Y 2
X
C b 0
C r0
C b 1
4 n s ~ 5 n s
1 4 n s ~ 1 5 n s
M C L K
As specified in the above data output timing diagram, the timing margin between video clock pin
(VCLK) and data pins (Y[7:0] or C[7:0]) is about 4ns ~ 5ns. This margin may be sufficient or not
according to how much video clock and data pins are delayed internally in the backend chip,
respectively. To safely latch the data output in the backend chip, it is recommended that data be
latched at negative edge of VCLK. The above timing margin diagram represents 16bit output interface,
but is also valid for 8bit output interface.
Output Data Format
Output Format is controlled by configuring Output Format register[31h]. Configurable options are
specified again for your reference.
Output Format [OUTFMT : 31h : 39h]
7
6
5
4
3
2
1
0
reserved
reserved
Cb First
Y First
8 Bit Output
reserved
YCbCr
4:4:4
YCbCr
4:2:2
0
0
1
1
1
0
0
1
Cb First
Cb pixel in front of Cr pixel in 16bit or 8bit video data output modes
Y First
Y pixel in front of Cb and Cr pixels in 8bit video output mode. This option is
meaningful only with 8bit output mode.
8 Bit Output
Image Data is produced only in Y[7:0]. C[7:0] should be discarded
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