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Confidential
HV7161SPA2
CMOS Image Sensor
With Image Signal Processing
Pin Function
System power supply
DVDDC
AVDDC
from digital power, I/O power and signals.
DVDDI
AVDDPH
properly from digital power, I/O power and signals.
DVDDIH
2.5V to 2.8V power supply for the input/output/bidirectional pad.
Note :
Attach a bypass capacitor near each power pin.
System ground
DGNDC
1.8V ground for the internal digital circuit.
AGNDC
1.8V or 2.5V to 2.8V ground for the internal analog circuit. Separate
properly from digital power, I/O power and signals.
DGNDI
1.8V ground for the input/output/bidirectional pad.
DGNDIH
2.5V to 2.8V ground for the input/output/bidirectional pad.
Input pins
RESETB
When RESETB pin is an active low input, an external reset is
generated. And all internal registers are initialized and are loaded by each default value.
It is required that reset period is holding for more than 4 MCLK clocks when ENB pin is
high level. Shorter period is not guaranteed to produce a reset scheme and make a
sensor be unstably operated. Active low RESETB pin generates all output pins except
VCLK pin to low level. VCLK pin is not affected to RESETB pin.
ENB
When ENB pin is an active high input, all functions of a sensor can be
normally operated and so all output data are valid. If ENB pin is a low level, a sensor
enters into a sleep mode and all functions are suspended. And all output pins hold each
previous value. Sleep mode register SCTRB[4] bit means a soft-power down and ENB
pin means a hard-power down. After RESETB pin is changed from a low to a high level,
ENB
pin should be changed from a low to a high level. At the external (ENB) power-down
mode, all output and bidirectional pins have a state of Hi-Z (high impedance). In addition
to power-down mode, Y[7:0] and C[7:0] pins have a state of Hi-Z during HSYNC pin is
low
level. To minimize a power consumption at the external hard power-down mode
(by
ENB pin), the sensor's main power should be turned off together.
MCLK
MCLK pin is a master clock of sensor and determines maximum
frame rate. This pin generates video clock (VCLK) and is supplied from an external clock
oscillator. Between the external clock oscillator and MCLK pin should be as near as
possible.
SCK
SCK is an input pin to be supplied I2C bus clock from master device
and sensor get to be a slave device. SCK clock frequency is able up to maximum
This document has a general product description and is subject to change without notice.
MagnaChip Semiconductor Ltd. does not assume any responsibility for use of circuits described
and no patent licenses are implied.
- 8 -
2005 MagnaChip Semiconductor Ltd.
1.8V power supply for the internal digital circuit.
1.8V power supply for the internal analog circuit. Separate properly
1.8V I/O power supply for the input/output/bidirectional pad.
2.5V to 2.8V power supply for the internal pixel array. Separate