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參數(shù)資料
| 型號： | HY29F002TT-90 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 2 Megabit (256K x 8), 5 Volt-only, Flash Memory |
| 中文描述： | 256K X 8 FLASH 5V PROM, 90 ns, PDSO32 |
| 封裝： | TSOP-32 |
| 文件頁數(shù)： | 6/38頁 |
| 文件大?。?/td> | 381K |
| 代理商： | HY29F002TT-90 |
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6
Rev. 4.1/May 01
HY29F002T
Table 3. HY29F002T Bus Operations Requiring High Voltage
1, 2
n
o
r
e
p
O
#
E
C
O
Notes:
1. L = V
, H = V
, X = Don
’
t Care. See DC Characteristics for voltage levels.
2. Address bits not specified are Don
’
t Care.
3. See text for additional information.
4. SA = sector address. See Table 1.
The
‘
Device Commands
’
section of this document
provides details on the specific device commands
implemented in the HY29F002T.
3
#
E
#
E
W
#
T
E
S
E
R
]
1
:
1
A
]
A
]
A
]
A
]
A
]
:
Q
D
t
e
P
r
e
S
L
V
D
I
X
H
A
S
4
V
D
I
X
X
X
X
t
r
e
e
n
U
y
p
m
t
e
n
U
r
e
e
T
S
V
D
I
V
D
I
X
H
X
V
D
I
X
X
X
X
S
X
X
X
V
D
I
X
X
X
X
X
X
e
d
o
C
r
a
n
a
M
L
L
H
H
X
V
D
I
L
L
L
D
A
x
0
e
d
o
C
e
c
e
D
L
L
H
H
X
V
D
I
L
L
H
0
B
x
0
r
e
e
P
c
V
S
n
o
o
n
d
e
e
n
U
L
L
H
H
A
S
4
V
D
I
L
H
L
0
0
x
0
d
e
e
P
1
0
x
0
Output Disable Operation
When the OE# input is at V
IH
, output data from the
device is disabled and the data bus pins are placed
in the high impedance state.
Standby Operation
When the system is not reading from or writing to
the HY29F002T, it can place the device in the
Standby mode. In this mode, current consump-
tion is greatly reduced, and the data bus outputs
are placed in the high impedance state, indepen-
dent of the OE# input. The Standby mode can
invoked using two methods.
The device enters the
CE# CMOS Standby
mode
if the CE# and RESET# pins are both held at V
CC
± 0.5V. Note that this is a more restricted voltage
range than V
IH
. If both CE# and RESET# are held
High, but not within V
CC
± 0.5V, the device will be
in the
CE# TTL Standby
mode, but the standby
current will be greater.
The device enters the
RESET# CMOS
Standby
mode when the RESET# pin is held at V
SS
± 0.5V.
If RESET# is held Low but not within V
SS
± 0.5V,
the HY29F002T will be in the
RESET# TTL
Standby
mode, but the standby current will be
greater. See Hardware Reset Operation section
for additional information on the reset operation.
The device requires standard access time (t
CE
) for
read access when the device is in either of the
standby modes, before it is ready to read data. If
the device is deselected during erasure or pro-
gramming, it continues to draw active current until
the operation is completed.
Hardware Reset Operation
The RESET# pin provides a hardware method of
resetting the device to reading array data. When
the RESET# pin is driven Low for the minimum
specified period, the device immediately termi-
nates any operation in progress, tri-states the data
bus pins, and ignores all read/write commands for
the duration of the RESET# pulse. The device also
resets the internal state machine to reading array
data. If an operation was interrupted by the as-
sertion of RESET#, it should be reinitiated once
the device is ready to accept another command
sequence to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse as described in the Standby Operation sec-
tion above.
If RESET# is asserted during a program or erase
operation, the internal reset operation is completed
within a time of t
READY
(during Automatic Algo-
rithms). The system can perform a read or write
operation after waiting for a minimum of t
READY
or
until t
RH
after the RESET# pin returns High, which-
ever is longer. If RESET# is asserted when a pro-
gram or erase operation is not executing, the re-
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