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參數(shù)資料

Rev. 0.52/Nov. 02 53

HY5PS12423(L)F

HY5PS12823(L)F

HY5PS121623(L)F

Power Down

When CKE goes low DDR-II DRAM entered power down mode. If power down command is issued during all bank idle

state, DRAM enter precharge power down mode. If power down command is issued when any particular row is active

states, DRAM enter active power down mode. Power down command is prohibited during any read or write burst

accesses. During power down mode, all input and output buffer is turned off except CK, CK and CKE, which means all

input signals are Don’t care. Power down mode is maintained by keep CKE low. Power-down duration is limited by the

refresh requirements of the device. Power down state is synchronously exited when CKE assert high. A valid, execut-

able command may be applied two clock cycles later.

/CK

CKE

tIS

NOP

CMD

Valid

NOP

Valid

No column access

in progress

Enter power down mode

Exit power down mode

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
HY5PS121623LF	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:32Mx16\|1.8V\|8K\|D43/D44/D54/D55\|DDR II SDRAM - 512M
HY5PS12421AF	制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421AF-C3	制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421AF-C4	制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421AF-E3	制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM

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