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參數(shù)資料

Rev. 0.52/Nov. 02 63

HY5PS12423(L)F

HY5PS12823(L)F

HY5PS121623(L)F

14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-

sitions through the DC region must be monotonic.

15. tDAL = (tDPL / tCK ) + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer. tCK

is equal to the actual system clock cycle time.

Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,

tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)

Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks

16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - BL/2 x

tCK.

The previous and This Page will be changed by the standardization result of Je-

dec Committee.

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
HY5PS121623LF	制造商:未知廠家制造商全稱(chēng):未知廠家功能描述:32Mx16\|1.8V\|8K\|D43/D44/D54/D55\|DDR II SDRAM - 512M
HY5PS12421AF	制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421AF-C3	制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421AF-C4	制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM
HY5PS12421AF-E3	制造商:HYNIX 制造商全稱(chēng):Hynix Semiconductor 功能描述:512Mb DDR2 SDRAM

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