參數(shù)資料
型號: HYB18T1G400AFL-3S
廠商: INFINEON TECHNOLOGIES AG
英文描述: 1 Gbit DDR2 SDRAM
中文描述: 1千兆位DDR2內(nèi)存
文件頁數(shù): 24/89頁
文件大?。?/td> 1752K
代理商: HYB18T1G400AFL-3S
Page 24 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
ODT Truth Tables
The ODT Truth Table shows which of the input pins are terminated depending on the state of address bit A10 and
A11 in the EMRS(1) for all three device organisations (x4, x8 and x16). To activate termination of any of these
pins, the ODT function has to be enabled in the EMRS(1) by address bits A6 and A2.
ODT timing modes
Depending on the operating mode synchronous or asynchronous ODT timings apply. Synchronous timings
(tAOND, tAOFD, tAON and tAOF) apply for all modes, when the on-die DLL is not disabled.
These modes are:
Active Mode
Standby Mode
Fast Exit Active Power Down Mode (with MRS bit A12 is set to “0”)
Asynchronous ODT timings (tAOFPD, tAONPD) apply when the on-die DLL is disabled.
These modes are:
Slow Exit Active Power Down Mode (with MRS bit A12 is set to “1”)
Precharge Power Down Mode
Input Pin
EMRS(1)
Address Bit A10
EMRS(1)
Address Bit A11
x4 components:
DQ0~DQ3
X
X
DQS
X
X
DQS
0
X
DM
X
X
x8 components:
DQ0~DQ7
X
X
DQS
X
X
DQS
0
X
RDQS
X
1
RDQS
0
1
DM
X
0
x16 components:
X
X
X
0
X
0
X
X
LDQ0~LDQ7
X
X
X
X
X
X
X
X
UDQ0~UDQ7
LDQS
LDQS
UDQS
UDQS
LDM
UDM
X = don’t care; 0 = bit set to low; 1 = bit set to high
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