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參數(shù)資料
| 型號： | HYB18T1G800AF-37 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 1 Gbit DDR2 SDRAM |
| 中文描述： | 1千兆位DDR2內(nèi)存 |
| 文件頁數(shù)： | 3/89頁 |
| 文件大小： | 1752K |
| 代理商： | HYB18T1G800AF-37 |
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HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 3 Rev. 1.02 May 2004
Rainer.Weidlich@Infineon.com
Features
High Performance:
1.8V ± 0.1V Power Supply
1.8 V ± 0.1V (SSTL_18) compatible) I/O
DRAM organisations with 4, 8 and 16 data in/outputs
Double Data Rate architecture: two data transfers per
clock cycle, eight internal banks for concurrent operation
CAS Latency: 3, 4 and 5
Burst Length: 4 and 8
Speed Sorts
-5
DDR2
-400
-3.7
DDR2
-533
-3S
DDR2
-667
-3
DDR2
-667
Units
Bin
(CL-tRCD-TRP)
3-3-3
4-4-4
5-5-5
4-4-4
tck
max. Clock Frequency
200
266
333
MHz
Data Rate
400
533
667
Mb/s/pin
CAS Latency (CL)
3
4
5
4
tck
tRCD
15
15
15
12
ns
tRP
15
15
15
12
ns
tRAS
40
45
45
45
ns
tRC
55
60
60
57
ns
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and DQS) are
transmitted / received with data. Edge aligned with
read data and center-aligned with write data
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe opera-
tion
Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
Data masks (DM) for write data
Posted CAS by programmable additive latency for better
command and data bus efficiency
Off-Chip-Driver impedance adjustment (OCD) and On-Die-
Termination (ODT) for better signal quality.
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving Power-
Down modes
Average Refresh Period 7.8μs at a T
CASE
lower than
85
o
C, 3.9μs between 85
o
C and 95
o
C
Strong and Weak Strength Data-Output Driver
1k page size for x 4 & x 8,
2k page size for x16
Lead-free Packages:
68 pin FBGA for x4 & x8 components
92 pin FBGA for x16 components
1.0 Description
The 1Gb Double-Data-Rate-2 (DDR2) DRAMs are high-speed
CMOS Double Data Rate 2 Synchronous DRAM devices con-
taining 1,073,741,824 bits and is internally configured as a
octal-bank DRAM. The 1Gb chip is organized as either 32Mbit
x 4 I/O x 8 banks, 16Mbit x 8 I/O x 8 banks or 8Mbit x 16 I/O x 8
banks device. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 667 Mb/sec/pin for gen-
eral applications.
The chip is designed to comply with all key DDR2 DRAM key
features: (1) posted CAS with additive latency, (2) write latency
= read latency -1, (3) normal and weak strength data-output
driver, (4) Off-Chip Driver (OCD) impedance adjustment and
(5) an ODT (On-Die Termination) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are latched
at the cross point of differential clocks (CK rising and CK fall-
ing). All I/Os are synchronized with a single ended DQS or dif-
ferential (DQS, DQS) pair in a source synchronous fashion. A
17 bit address bus for x 4 and x 8 organised components and a
16 bit address bus for x16 components is used to convey row,
column and bank address information in a RAS / CAS multi-
plexing style.
The DDR2 devices operate with a 1.8V +/-0.1V power supply
and are available in FBGA packages.
An Auto-Refresh and Self-Refresh mode is provided along with
various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
.
DATASHEET Rev. 1.02 (05.04)
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| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
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