參數(shù)資料
型號(hào)： HYB18T1G800AF-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 1 Gbit DDR2 SDRAM
中文描述： 1千兆位DDR2內(nèi)存
文件頁數(shù)： 18/89頁
文件大小： 1752K
代理商： HYB18T1G800AF-5
Page 18 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
A0 is used for DLL enable or disable. A1 is used for enabling half-strength data-output driver. A2 and A6 enables
ODT (On-Die termination) and sets the Rtt value. A3~A5 are used for additive latency settings and A7 ~ A9
enables the OCD impedance adjustment mode. A10 enables or disables the differential DQS and RDQS signals,
A11 disables or enables RDQS. Address bit A12 have to be set to “l(fā)ow” for normal operation. With A12 set to
“high” the SDRAM outputs are disabled and in Hi-Z. “High” on BA0 and “l(fā)ow” for BA1 and BA2 have to be set to
access the EMRS(1). A13 and all “higher” address bits have to be set to “l(fā)ow” for compatibility with other DDR2
memory products with higher memory densities. Refer to the table for specific codes on the previous page.
Single-ended and Differential Data Strobe Signals
The following table lists all possible combinations for DQS, DQS, RDQS, RQDS which can be programmed by
A10 & A11 address bits in EMRS(1). RDQS and RDQS are available in x8 components only. If RDQS is enabled
in x8 components, the DM function is disabled. RDQS is active for reads and don’t care for writes:
DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering
Self-Refresh operation and is automatically re-enabled and reset
upon exit of Self-Refresh operation. Any time the
DLL is reset, 200 clock cycles must occur before a Read command can be issued to allow time for the internal
clock to be synchronized with the external clock. Less clock cycles may result in a violation of the tAC or tDQSCK
parameters.
Output Disable (Qoff)
Under normal operation, the DRAM outputs are enabled during Read operation for driving data (Qoff bit in the
EMRS(1) is set to 0). When the Qoff bit is set to 1, the DRAM outputs will be disabled. Disabling the DRAM out-
puts allows users to measure IDD currents during Read operations, without including the output buffer current.
EMRS(1)
Stobe Function Matrix
Signaling
A11
(RDQS Enable)
A10
(DQS Enable)
RDQS/DM
RDQS
DQS
DQS
0 (Disable)
0 (Enable)
DM
Hi-Z
DQS
DQS
differential DQS signals
0 (Disable)
1 (Disable)
DM
Hi-Z
DQS
Hi-Z
single-ended DQS signals
1 (Enable)
0 (Enable)
RDQS
RDQS
DQS
DQS
differential DQS signals
1 (Enable)
1 (Disable)
RDQS
Hi-Z
DQS
Hi-Z
single-ended DQS signals
相關(guān)PDF資料
PDF描述
HYB18T1G800AFL-3 1 Gbit DDR2 SDRAM
HYB18T1G800AFL-37 1 Gbit DDR2 SDRAM
HYB18T1G800AFL-3S 1 Gbit DDR2 SDRAM
HYB18T1G800AFL-5 1 Gbit DDR2 SDRAM
HYB18T1G800TC-3 MEMORY SPECTRUM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T1G800BF-3S 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
HYB18T256400AF-3.7 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60
HYB18T256400AF-5 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA
HYB18T256800AF-5 制造商:Infineon Technologies AG 功能描述:
HYB18T512161BF-25 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA
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