參數(shù)資料
型號： HYB18T1G800AF-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 1 Gbit DDR2 SDRAM
中文描述： 1千兆位DDR2內(nèi)存
文件頁數(shù)： 73/89頁
文件大小： 1752K
代理商： HYB18T1G800AF-5
HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 73 Rev. 1.02 May 2004
6.2 IDD Measurement Conditions
(VDDQ = 1.8V
±
0.1V; VDD = 1.8V
±
0.1V)
Symbol
Parameter/Condition
IDD0
Operating Current
-
One bank Active - Precharge
tCK =tCK(IDD).; tRC = tRC(IDD); tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands.
Address and control inputs are SWITCHING; Data bus inputs are SWITCHING;
Operating Current
-
One bank Active - Read - Precharge
IOUT = 0 mA; BL = 4, tCK = tCK(IDD), tRC = tRC(IDD); tRAS = tRASmin(IDD); tRCD = tRCD(IDD), CL = CL(IDD).;AL = 0;
CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING, Data bus inputs are SWITCHING;
Precharge Power-Down Current:
All banks idle; CKE is LOW; tCK = tCK(IDD).; Other control and address inputs are STA-
BLE, Data Bus inputs are FLOATING.
Precharge Standby Current
: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD).; Other control and address bus inputs
are SWICHTING; Data bus inputs are SWITCHING.
Precharge Quiet Standby Current
: All banks idle; CS is HIGH;
CKE is HIGH; tCK = tCK(IDD).; Other control and address bus
inputs are STABLE; Data bus inputs are FLOATING.
Active Power-Down Current
: All banks open; tCK = tCK(IDD).;CKE is LOW; Other control and address inputs are STABLE;
Data Bus inputs are FLOATING. MRS A12 bit is set to “0”(Fast Power-down Exit);
Active Power-Down Current
: All banks open; tCK = tCK(IDD).;CKE is LOW; Other control and address inputs are STABLE;
Data Bus inputs are FLOATING. MRS A12 bit is set to “1”(Slow Power-down Exit);
Active Standby Current
: All banks open; tCK = tCK(IDD); tRAS = tRASmax(IDD).; tRP = tRP(IDD)., CKE is HIGH; CS is
HIGH between valid commands; Other control and address inputs are SWITCHING; Data Bus inputs are SWITCHING.
Operating Current - Burst Read:
All banks open;
Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD).;
tRAS = tRASmax(IDD)., tRP = tRP(IDD)., CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCH-
ING; Data bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write:
All banks open;
Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD).;
tRAS = tRASmax(IDD)., tRP = tRP(IDD).;CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCH-
ING; Data Bus inputs are SWITCHING;
Burst Auto-Refresh Current
: tCK = tCK(IDD); Refresh command every tRFC = tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING.
Distributed Auto-Refresh Current
: tCK = tCK(IDD).; Refresh command every tREFI=7.8 μs interval; CKE is LOW and CS is
HIGH between valid commands; Other control and address inputs are SWITCHING; Data bus inputs are SWITCHING
Self-Refresh Current
: CKE
≤
0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING;
Data Bus inputs are FLOATING.
Eight Bank Interleave Read Current:
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P(0)
IDD3P(1)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL=CL(IDD), AL = tRCD(IDD) -1*tCK(IDD);
tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is high between valid com-
mands, Address bus inputs are STABLE during DESELECTS; Data bus is SWITCHING.
2. Timing pattern for x4 and x8 components:
-
DDR2 -400
: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7 (16 clocks)
-
DDR2 -533
: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D (20 clocks)
-
DDR2 -667
: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D (26 clocks)
3. Timing pattern for x16 components:
-
DDR2 -400
: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D (20 clocks)
-
DDR2 -533:
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D (28 clocks)
-
DDR2 -667:
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D (34 clocks)
4. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
2. Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
3. Definitions for IDD:
LOW is defined as VIN <= VILAC(max.); HIGH is defined as VIN >= VIHAC(min.);
STABLE is defined as inputs are stable at a HIGH or LOW level
FLOATING is defined as inputs are VREF = VDDQ / 2
SWITCHING is defined as:
Inputs are changing between HIGH and LOW every other clock (once per two clocks) for address and control signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including mask or strobes.
4. Timing parameter values for IDD current measurements are defined in the following table.
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