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參數(shù)資料
| 型號(hào)： | HYB18T1G800AF-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 1 Gbit DDR2 SDRAM |
| 中文描述： | 1千兆位DDR2內(nèi)存 |
| 文件頁數(shù)： | 59/89頁 |
| 文件大小： | 1752K |
| 代理商： | HYB18T1G800AF-5 |
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HYB18T1G400/800/160AF
1Gb DDR2 SDRAM
INFINEON Technologies
Page 59 Rev. 1.02 May 2004
2.11 Other Commands
2.11.1 No Operation Command (NOP)
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of
the No Operation Command is to prevent the SDRAM from registering any unwanted commands between opera-
tions. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising
edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as
a burst read or write cycle.
2.10 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command occurs
when CS is brought high, the RAS, CAS, and WE signals become don’t care.
2.12 Input Clock Frequency Change
During operation the DRAM input clock frequency can be changed under the following conditions:
a) During Self-Refresh operation
b) DRAM is in precharged power-down mode and ODT is completely turned off.
The DDR2-SDRAM has to be in Precharged Power-down mode and idle. ODT must be already turned off and
CKE must be at a logic “l(fā)ow” state. After a minimum of two clock cycles after tRP and tAOFD have been satisfied
the input clock frequency can be changed. A stable new clock frequency has to be provided, before CKE can be
changed to a “high” logic level again. After tXP has been satisfied a DLL RESET command via EMRS(1) has to be
issued. During the following DLL re-lock period of 200 clock cycles, ODT must remain off. After the DLL-re-lock
period the DRAM is ready to operate with the new clock frequency.
Example:
Input frequency change during Precharge Power-Down mode
NOP
NOP
T0
T2
T1
T3
T4
Tx
Tx+1
Ty
NOP
NOP
NOP
NOP
NOP
DLL
RESET
Ty+2
Ty+3
Frequency Change
occurs here
NOP
NOP
Frequ.Ch.
Tz
tXP
Stable new clock
before power-down exit
tRP
tAOFD
Minimum 2 clocks
required before
changing the frequency
Ty+1
NOP
Valid
Command
200 clocks
ODT is off during
DLL RESET
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| HYB18T1G800BF-3S | 功能描述:IC DDR2 SDRAM 1GBIT 68TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
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