參數(shù)資料
型號(hào)： HYB18T256160AF-37
廠(chǎng)商： INFINEON TECHNOLOGIES AG
英文描述： 256 Mbi t DDR2 SDRAM
中文描述： 256姆噸DDR2內(nèi)存
文件頁(yè)數(shù)： 39/90頁(yè)
文件大?。?/td> 1246K
代理商： HYB18T256160AF-37
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
INFINEON Technologies
Page 39 Rev. 1.02 May 2004
2.6.5 Write Data Mask
One write data mask input (DM) for x4 and x8 components and two write data mask inputs (LDM, UDM) for x16
components are supported on DDR2 SDRAM’s, consistent with the implementation on DDR SDRAM’s. It has
identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally
loaded identically to data bits to insure matched system timing. Data mask is not used during read cycles. If DM is
high during a write burst coincident with the write data, the write data bit is not written to the memory. For x8 com-
ponents the DM function is disabled, when RDQS / RDQS are enabled by EMRS(1).
.
.
Write Data Mask Timing
Burst Write Operation with Data Mask: RL = 3 (AL = 0, CL = 3), WL = 2, tWR = 3, BL = 4
DQS,
DQS
DQS
DQS
t
DQSH
t
DQSL
t
WPRE
WPST
t
DQ
Din
Din
Din
Din
t
DS
DH
t
DM
don't care
NOP
NOP
NOP
NOP
NOP
W RITE A
T0
T2
T1
T3
T4
T5
T6
T7
T9
WL = RL-1 = 2
DM
CMD
DQ
NOP
tW R
<= tDQSS
Precharge
Bank A
Activate
tRP
DQS,
DQS
DM
DIN A0 DIN A1
DIN A3
DIN A2
CK, CK
相關(guān)PDF資料
PDF描述
HYB18T256160AF-5 256 Mbi t DDR2 SDRAM
HYB18T256160AL-3S 256 Mbi t DDR2 SDRAM
HYB18T256400AF 256 Mbi t DDR2 SDRAM
HYB18T256400AF-3 256 Mbi t DDR2 SDRAM
HYB18T256400AF-37 256 Mbi t DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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