參數(shù)資料
型號(hào)： HYB18T256160AF-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256 Mbi t DDR2 SDRAM
中文描述： 256姆噸DDR2內(nèi)存
文件頁(yè)數(shù)： 60/90頁(yè)
文件大?。?/td> 1246K
代理商： HYB18T256160AF-37
Page 60 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
2.13 Asynchronous CKE Low Reset Event
In a given system, Asynchronous Reset event can occur at any time without prior knowledge. In this situation,
memory controller is forced to drop CKE asynchronously low, immediately interrupting any valid operation. DRAM
requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE asynchronously
drops “l(fā)ow” during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If
this event occurs, the memory controller must satisfy a time delay (tdelay) before turning off the clocks. Stable
clocks must exist at the input of DRAM before CKE is raised “high” again. The DRAM must be fully re-initialized as
described the initialization sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the
initialization sequence. See AC timing parametric table for tdelay specification.
Asynchronous CKE Low Event
CKE
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
tdelay
CK, CK
stable clocks
相關(guān)PDF資料
PDF描述
HYB18T256160AF-5 256 Mbi t DDR2 SDRAM
HYB18T256160AL-3S 256 Mbi t DDR2 SDRAM
HYB18T256400AF 256 Mbi t DDR2 SDRAM
HYB18T256400AF-3 256 Mbi t DDR2 SDRAM
HYB18T256400AF-37 256 Mbi t DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T256400AF-3.7 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60
HYB18T256400AF-5 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA
HYB18T256800AF-5 制造商:Infineon Technologies AG 功能描述:
HYB18T512161BF-25 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA
HYB18T512400AF-5 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA
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