參數(shù)資料
型號(hào)： HYB18T256160AL-3S
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256 Mbi t DDR2 SDRAM
中文描述： 256姆噸DDR2內(nèi)存
文件頁數(shù)： 37/90頁
文件大?。?/td> 1246K
代理商： HYB18T256160AL-3S
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
INFINEON Technologies
Page 37 Rev. 1.02 May 2004
The minimum number of clocks from the burst write command to the burst read command is
(CL - 1) +BL/2 + tWTR
where tWTR is the write-to-read turn-around time tWTR expressed in clock cycles. The tWTR is not a write recov-
ery time (tWR) but the time required to transfer 4 bit write data from the input buffer into sense amplifiers in the
array.
Burst Write Operation: RL = 3 (AL = 0, CL = 3), WL = 2, BL = 4
Burst Write followed by Burst Read: RL = 5 (AL = 2, CL = 3), WL = 4, twitter = 2, BL = 4
NOP
NOP
NOP
NOP
NOP
W RITE A
Post CAS
T0
T2
T1
T3
T4
T5
T6
T7
T9
WL = RL-1 = 2
BW322
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
tW R
Completion of
the Burst Write
<= tDQSS
Precharge
Bank A
Activate
tRP
DQS,
DQS
CK, CK
NOP
NOP
NOP
NOP
NOP
READ A
Post CAS
BWBR
CMD
DQ
NOP
DIN A0 DIN A1 DIN A2 DIN A3
AL=2
tW TR
CL=3
NOP
NOP
T0
T2
T1
T3
T4
T5
T6
T7
T8
T9
W rite to Read = (CL - 1)+ BL/2 +tW TR(2) = 6
DQS,
DQS
W L = RL - 1 = 4
RL=5
CK, CK
相關(guān)PDF資料
PDF描述
HYB18T256400AF 256 Mbi t DDR2 SDRAM
HYB18T256400AF-3 256 Mbi t DDR2 SDRAM
HYB18T256400AF-37 256 Mbi t DDR2 SDRAM
HYB18T256400AF-3S 256 Mbi t DDR2 SDRAM
HYB18T256400AF-5 256 Mbi t DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T256400AF-3.7 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60
HYB18T256400AF-5 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA
HYB18T256800AF-5 制造商:Infineon Technologies AG 功能描述:
HYB18T512161BF-25 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA
HYB18T512400AF-5 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA
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