Page 4 Rev. 1.02 May 2004
INFINEON Technologies
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
1.1 Ordering Information
1.2 Pin Description
1.2.1 x4 Components
Symbol
Part Number
CAS
Latency
Clock
(MHz)
Speed
Sort
DRAM Organisation
Package
HYB18T256400AF(L)-5
3, 4 & 5
200
DDR2-400
4 banks x 16 Mbits x 4
60 pin FBGA
HYB18T256800AF(L)-5
4 banks x 8 Mbits x 8
60 pin FBGA
HYB18T256160AF(L)-5
4 banks x 4 Mbits x 16
84 pin FBGA
HYB18T256400AF(L)-3.7
4 & 5
266
DDR2-533
4 banks x 16 Mbits x 4
60 pin FBGA
HYB18T256800AF(L)-3.7
4 banks x 8 Mbits x 8
60 pin FBGA
HYB18T256160AF(L)-3.7
4 banks x 4 Mbits x 16
84 pin FBGA
HYB18T256400AF(L)-3
4 & 5
333
DDR2-667
4 banks x 16 Mbits x 4
60 pin FBGA
HYB18T256800AF(L)-3
4 banks x 8 Mbits x 8
60 pin FBGA
HYB18T256160AF(L)-3
4 banks x 4 Mbits x 16
84 pin FBGA
HYB18T256400AF(L)-3S
5
4 banks x 16 Mbits x 4
60 pin FBGA
HYB18T256800AF(L)-3S
4 banks x 8 Mbits x 8
60 pin FBGA
HYB18T256160A(L)-3S
4 banks x 4 Mbits x 16
84 pin FBGA
Notes:
1) For product nomenclature see section 10 of this datasheet
2) Versions with an “L” in the part numbers are Low Power versions of the standard component with reduced IDD6 Self-Refresh
current. See section 6.1 for IDD current specifications.
3) All FBGA packages are lead-free.
Function
Symbol
Function
A0~A12
Row Address Inputs
DQS, DQS
Differential Data Strobes
A0~A9,A11
Column Address Inputs
NC
No Connection (Chip to Pin)
BA0, BA1
Bank Address Inputs
Column Address Input
for Auto-Precharge
Chip Select
VDD
Supply Voltage
A10/AP
VSS
Ground
CS
VDDQ
Supply Voltage for DQ
RAS
Row Address Strobe
VSSQ
Ground for DQs
CAS
Column Address Strobe
VDDL
Supply Voltage for DLL
WE
Write Enable
VSSDL
Ground for DLL
Reference Voltage for SSTL
Inputs
On Die Termination Enable
DQ0~DQ3
Data Inputs/Outputs (x4)
VREF
CKE
Clock Enable
ODT
CK, CK
Differential Clock Inputs
RFU
Reserved for future use
DM
Data Input Mask
NC
Not Connected