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參數(shù)資料
| 型號： | HYB514175BJ-50 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 256k x 16-Bit EDO-DRAM |
| 中文描述： | 256K X 16 EDO DRAM, 50 ns, PDSO40 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-40 |
| 文件頁數(shù)： | 7/22頁 |
| 文件大?。?/td> | 177K |
| 代理商： | HYB514175BJ-50 |
HYB 514175BJ-50/-55/-60
256k
×
16 EDO-DRAM
Semiconductor Group
7
1998-10-01
RAS hold time
t
RSH
t
CSH
t
CRP
t
T
t
REF
13
–
13
–
15
–
ns
CAS hold time
40
–
45
–
50
–
ns
CAS to RAS precharge time
5
–
5
–
5
–
ns
Transition time (rise and fall)
1
50
1
50
1
50
ns
7
Refresh period
–
16
–
16
–
16
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
OEA
t
RAL
t
RCS
t
RCH
–
50
–
55
–
60
ns
8, 9
Access time from CAS
–
13
–
13
–
15
ns
8, 9
Access time from column address
–
25
–
25
–
30
ns
8, 10
OE access time
–
13
–
13
–
15
ns
Column address to RAS lead time
25
–
25
–
30
–
ns
Read command setup time
0
–
0
–
0
–
ns
Read command hold time
Read command hold time ref. to RAS
t
RRH
CAS to output in low-Z
Output buffer turn-off delay from CAS
t
OFF
Output buffer turn-off delay from OE
0
–
0
–
0
–
ns
11
0
–
0
–
0
–
ns
11
t
CLZ
0
–
0
–
0
–
ns
8
0
13
0
13
0
15
ns
12
t
OEZ
t
DZO
t
CDD
t
ODD
0
13
0
13
0
15
ns
12
Data to OE low delay
0
–
0
–
0
–
ns
13
CAS high to data delay
10
–
10
–
13
–
ns
14
OE high to data delay
10
–
10
–
13
–
ns
14
Write Cycle
Write command hold time
t
WCH
t
WP
t
WCS
t
RWL
t
CWL
t
DS
t
DH
t
DZC
8
–
8
–
10
–
ns
Write command pulse width
8
–
8
–
10
–
ns
Write command setup time
0
–
0
–
0
–
ns
15
Write command to RAS lead time
13
–
13
–
15
–
ns
Write command to CAS lead time
13
–
13
–
15
–
ns
Data setup time
0
–
0
–
0
–
ns
16
Data hold time
8
–
8
–
10
–
ns
16
Data to CAS low delay
0
–
0
–
0
–
ns
13
AC Characteristics
(cont’d)5, 6
T
A
= 0 to 70
°
C;
V
SS
= 0 V;
V
CC
= 5 V
±
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit Note
-50
-55
-60
min. max. min. max. min. max.
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| HYB514400BT-70 | RP12 (A) Series - Powerline Regulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 3.3V; 2:1 Wide Input Voltage Range; 12 Watts Output Power; 1.6kVDC Isolation; UL Certified; Over Current Protection; Five-Sided Shield; Standard DIP24 and SMD-Pinning; Efficiency to 88% |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB514175BJ-50- | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256k x 16-Bit EDO-DRAM |
| HYB514175BJ-55 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256k x 16-Bit EDO-DRAM |
| HYB514175BJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:256k x 16-Bit EDO-DRAM |
| HYB514175BJL-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
| HYB514175BJL-55 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 EDO Page Mode DRAM |
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