參數(shù)資料
型號: HYB514265BJ-45
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 256K x 16-Bit EDO-Dynamic RAM
中文描述: 256K X 16 EDO DRAM, 45 ns, PDSO40
文件頁數(shù): 11/28頁
文件大?。?/td> 1324K
代理商: HYB514265BJ-45
HYB 5(3)14265BJ(L)-400/-40/-45/-50
256K x 16 EDO-DRAM
Semiconductor Group
11
AC Characteristics
5)6)
T
A
= 0 to 70 C,
t
T
= 2 ns
Parameter
16E
Symbol
Limit Values
Unit
Note
-45
-50
min.
max.
min.
max.
Common Parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
CP
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
t
REF
79
89
ns
RAS precharge time
30
35
ns
RAS pulse width
45
10k
50
10k
ns
CAS pulse width
7
10k
8
10k
ns
CAS precharge time
7
8
ns
Row address setup time
0
0
ns
Row address hold time
7
8
ns
Column address setup time
0
0
ns
Column address hold time
7
8
ns
RAS to CAS delay time
11
33
12
37
ns
RAS to column address delay
9
23
10
25
ns
RAS hold time
12
13
ns
CAS hold time
36
40
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
1
50
1
50
ns
7
Refresh period
16
16
ms
Refresh period (L-version only)
128
128
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
OEA
t
RAL
t
RCS
t
RCH
t
RRH
t
CLZ
45
50
ns
8, 9
Access time from CAS
12
13
ns
8, 9
Access time from column address
22
25
ns
8,10
OE access time
12
13
ns
Column address to RAS lead time
23
25
ns
Read command setup time
0
0
ns
Read command hold time
0
0
ns
11
Read command hold time referenced to RAS
0
0
ns
11
CAS to output in low-Z
0
0
ns
8
相關(guān)PDF資料
PDF描述
HYB314265BJ-45 256K x 16-Bit EDO-Dynamic RAM
HYB514265BJ-50 256K x 16-Bit EDO-Dynamic RAM
HYB314265BJ-50 256K x 16-Bit EDO-Dynamic RAM
HYB314265BJL-45 256K x 16-Bit EDO-Dynamic RAM
HYB314265BJL-50 256K x 16-Bit EDO-Dynamic RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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