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| 型號： | IA6805E2PLC44IR0 |
| 廠商： | Innovasic Semiconductor |
| 文件頁數(shù)： | 28/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 5MHZ 44PLCC |
| 標準包裝： | 270 |
| 芯體尺寸： | 8-位 |
| 速度： | 5MHz |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 20 |
| 程序存儲器類型： | 外部程序存儲器 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
I/O Signal Description
The table below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
S IG N A L N A M E
I/O
DE S CRIP T IO N
V DD a nd V S S
(P ow e r a n d G roun d)
N/A
Sourc e :
T he s e tw o pins prov ide p ow er to th e c hip .
V DD pro v ides +5 v o lts (± 0 .5 )
pow e r and V SS is ground .
R ESET _ n
(R eset)
I
TT L : Inp ut pin that c an be us ed to res et the M P U 's intern al state by pulling the res et_n
pin lo w .
IR Q _ n
(Inte rrupt R e que s t)
I
TT L : Input p in th at is lev e l and e dge sen s itiv e. C an be us ed to re ques t an interrup t
se quen ce.
L I
(Loa d Ins truc tion)
O
T T L w ith s le w ra te c o n tro l: O utp ut pin used to ind ic ate tha t a n ext opc ode fetc h is in
progres s.
U s ed on ly for c e rtain d ebug gin g a nd te s t s ys tem s .
N o t co nnec ted in
norm a l op eration. O v e rlaps D ata S trobe (D S ) s ign al. T his output is cap able of d riv ing
one s ta ndard T T L load an d 5 0pF .
D S
(D a ta S tro b e )
O
T T Lw iths le w ra te c o n tro l: O utp ut pin us ed to trans fe r data to o r fro m a p eriphe ra l
or m e m ory. D S occ urs a nytim e the M P U do es a da ta re ad or w rite and during data
tran sfer to or from internal m em ory. D S is a v ailab le at fOS C 5 w h en the M P U is not in
the W A IT o r S T O P m ode. T his outpu t is c ap able of driv ing one s ta ndard T T L loa d and
130 pF .
R W _ n
(R ead /W rite )
O
T T L w ith s le w ra te c o n tro l: O utpu t pin us ed to indicate the directio n of da ta trans fe r
fro m inte rna l m e m ory, I/O registers, and e x tern al p eriph era l dev ic es a nd m em ories .
Indicates to a selected pe ripheral w h ether the M P U is to re ad (R W _n high) or w rite
(R W _ n low ) d ata o n the n ext d ata strob e.
T his ou tpu t is c ap able o f driv in g one
stand ard T T L load and 13 0pF .
A S
(A d d ress S tro b e)
O
T T Lw iths le w ra te c o n tro l:
O utput s trobe us ed to indicate th e pres ence of an
add re ss on the 8 -bit m ultiplex ed bu s . T he A S line is us ed to d em ultiplex the eigh t
least s ign ificant add re ss bits from the data bus . A S is a v ailab le at fOS C 5 w h e n th e
M P U is not in th e W A IT or S T O P m od es.
T his ou tpu t is c apab le of d riv ing one
stand ard T T L load and 13 0pF .
PA 0 -PA 7 /PB 0 -PB 7
(Inp ut/O utput Lin e s )
I/O
T T Lw iths le w ra te c o n tro l: T hese 1 6 lin es con s titute Inpu t/O utput p orts A a nd B .
E ac h line is ind iv idua lly program m ed to be eith er a n input or output unde r s oftw are
c o n tro l o f th e Da ta Dire c tio n Re g is te r (DDR) a s s h o w n b e lo w in Ta b le 1 and Fig ure 2 .
T h e po rt I/O is p rog ram m ed by w ritin g the correspo nding bit in the D D R to a "1" fo r
outpu t and a "0" for inp ut. In the ou tp ut m od e the bits are latc hed an d appea r on the
co rres ponding ou tpu t pins . A ll the D D R 's are in itia lized to a "0" o n res et. T he ou tpu t
port re gis ters are no t initialized on reset.
E a ch output is ca pable o f driv ing one
stand ard T T L load and 50 pF .
A 8 -A 1 2
(H igh O rde r A ddre s s
Line s )
O
T T Lw iths le w ra te c o n tro l:
T hese fiv e outpu ts con s titute the h igh er order non -
m ultip lex ed addres s lines . E ach outpu t is c apab le of driv ing one s tan dard T T L load
and 1 30pF .
B 0 -B 7
(A d d ress/D ata B u s)
I/O
T T Lw iths le w ra te c o n tro l:
T hese bi-direc tiona l lines con s titute the low er orde r
add re sse s and data.
T h ese line s are m ultiple x ed w ith ad dre s s pres ent a t addres s
strobe tim e and data prese nt a t da ta strob e tim e . W hen in the d ata m ode , thes e lin es
are bi-directional, tra nsferring d ata to an d from m em ory a nd perip heral d ev ices as
indicated by the R W _n pin.
A s outputs, the s e lin es are c ap able o f driv in g one
stand ard T T L load and 13 0 p F.
Tim e r
I
TT L : Input u s ed to c ontrol the internal tim er/c ounter circ uitry.
O S C 1 , O S C 2
(S y ste m C lo ck)
T T L O s c illa to r input/output: T hese pins pro v id e c ontrol input for the o n-c hip c loc k
os cillator circ uits .
E ither a c rystal or ex te rna l clock is c on nected to thes e p in s to
prov ide a system clock . T he c rystal co nnec tion is s how n in Fig ure 3 .T h e O S C 1 to
bus trans itions for s ys tem de s igns us ing osc illato rs slow er than 5M H z is sho w n in
Figure 4 .
Crys ta l
T h e c irc u it s h o w n in Fig ure 3 is rec om m e nded w hen us in g a c rys ta l.
A n ex terna l
C M O S osc illato r is re c om m ende d w h en us in g crys tals outside the s pecifie d ran ges .
T o
m inim ize
output
distortion
and
start-up
s ta bilization
tim e,
the
c rys ta l
and
co m pon ents shou ld be m o unted as clos e to th e inp ut pins as po ss ible.
E x tern al C loc k
W hen an external clock is us ed, it sho uld be app lied to the O S C 1 input w ith the O S C 2
input not c onnec te d, as s how n in Figu re 3 .
I/O
Table 1
Copyright 2007
IA211081401-03
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