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參數(shù)資料
| 型號： | IA6805E2PLC44IR0 |
| 廠商： | Innovasic Semiconductor |
| 文件頁數(shù)： | 8/33頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 5MHZ 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 270 |
| 芯體尺寸： | 8-位 |
| 速度： | 5MHz |
| 外圍設(shè)備： | POR |
| 輸入/輸出數(shù)： | 20 |
| 程序存儲器類型： | 外部程序存儲器 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
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IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
Timer:
The MPU contains a single 8-bit software programmable counter driven by a 7-bit software
programmable prescaler. The counter may be loaded under program control and decrements
to zero. When the counter decrements to zero, the timer interrupt request bit in the timer
control register (TCR7) is set. Figure 13 shows a block diagram of the timer. If the timer
mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, an
interrupt request is generated. After completion of the current instruction, the current state
of the machine is pushed onto the stack. The timer interrupt vector address is then fetched
from locations $1FF8 and $1FF9 and the interrupt routine is executed, unless the MPU was
in the WAIT mode in which case the interrupt vector address in locations $1FF6 and $1FF7
is fetched. Power-On-Reset causes the counter to set to $FF.
NOTE: 1. Prescaler and counter are clocked on the falling edge of the internal
clock (AS) or external input.
2. Counter is written to during Data Strobe (DS) and counts down continuously.
TIMER
(PIN 37)
TCR4
TCR5
TCR3
TCR2
TCR1
TCR0
2 - TO - 1
MUX
PRESCALER
(7 BITS)
COUNTER
(8 BITS)
INTERRUPT
CONTROL
WRITE
READ
INT
CLK
EXT
CLK
INTERRUPT
INTERNAL_n / EXTERNAL
INTERNAL
CLOCK
ENABLE /
DISABLE_n
TIMER_n
SETTING TCR3 CLEARS
PRESCALER TO ÷ 1
SOFTWARE FUNCTIONS
Figure 13. Timer Block Diagram
Copyright 2007
IA211081401-03
www.Innovasic.com
Customer Support:
Page 16 of 33
1-888-824-4184
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