參數(shù)資料
型號(hào)： IBM25NPE405H-3BA266CZ
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA580
封裝： 35 MM, PLASTIC, EBGA-580
文件頁(yè)數(shù)： 39/74頁(yè)
文件大?。?/td> 1423K
代理商： IBM25NPE405H-3BA266CZ
Preliminary
PowerNP NPe405H Embedded Processor Data Sheet
44
Signal Functional Description (Part 1 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
PCI Interface
PCIAD0:31
PCI Address/Data bus. Multiplexed address and data bus
I/O
5V tolerant
3.3V PCI
PCIC3:0[BE3:0]
PCI bus command or Byte Enable
I/O
5V tolerant
3.3V PCI
PCIParity
PCI Parity. Parity is even across PCIAD0:31 and
PCIC0:3[BE0:3]. PCIParity is valid one cycle after either an
address or data phase. The PCI device that drove
PCIAD0:31 is responsible for driving PCIParity on the next
PCI bus clock.
I/O
5V tolerant
3.3V PCI
PCIFrame
Driven by the current PCI bus master to indicate the
beginning and duration of a PCI access.
I/O
5V tolerant
3.3V PCI
4
PCIIRDY
Driven by the current PCI bus master. Assertion of
PCIIRDY indicates that the PCI initiator is ready to transfer
data.
I/O
5V tolerant
3.3V PCI
4
PCITRDY
The target of the current PCI transaction drives PCITRDY.
Assertion of PCITRDY indicates that the PCI target is
ready to transfer data.
I/O
5V tolerant
3.3V PCI
4
PCIStop
The target of the current PCI transaction can assert
PCIStop to indicate to the requesting PCI master that it
wants to end the current transaction.
I/O
5V tolerant
3.3V PCI
4
PCIDevSel
Driven by the target of the current PCI transaction. A PCI
target asserts PCIDevSel when it has decoded an address
and command encoding and claims the transaction.
I/O
5V tolerant
3.3V PCI
4
PCIIDSel
Used during configuration cycles to select the PCI slave
interface for configuration
I
5V tolerant
3.3V PCI
5
PCISErr
Used for reporting address parity errors or catastrophic
failures detected by a PCI target.
I/O
5V tolerant
3.3V PCI
4
PCIPErr
Used for reporting data parity errors on PCI transactions.
PCIPErr is driven active by the device receiving
PCIAD0:31, PCIC0:3[BE0:3], and PCIParity, two PCI
clocks following the data in which bad parity is detected.
I/O
5V tolerant
3.3V PCI
4
PCIClk
Used as the asynchronous PCI clock.
I
5V tolerant
3.3V PCI
PCIReset
PCI specific reset
O
5V tolerant
3.3V PCI
PCIINT
PCI Interrupt. Open-drain output (two states; 0 or open
circuit).
O
5V tolerant
3.3V PCI
PCIReq0[Gnt]
Req0 when internal arbiter is used, or Gnt when external
arbiter is used.
I
5V tolerant
3.3V PCI
PCIReq1:5
Used as PCIReq1:5 input when internal arbiter is used
I
5V tolerant
3.3V PCI
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參數(shù)描述
IBM25NPE405L-3FA133C 制造商:AMCC 制造商全稱(chēng):Applied Micro Circuits Corporation 功能描述:PowerNP
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