參數(shù)資料
型號(hào)： IBM25NPE405H-3BA266CZ
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA580
封裝： 35 MM, PLASTIC, EBGA-580
文件頁(yè)數(shù)： 44/74頁(yè)
文件大?。?/td> 1423K
代理商： IBM25NPE405H-3BA266CZ
Preliminary
PowerNP NPe405H Embedded Processor Data Sheet
49
[PerWE]
Peripheral write enable. Low when any of the four PerWBE
signals are low.
I/O
5V tolerant
3.3V LVTTL
7
PerCS0
[PerCS1:7]
Peripheral Chip Selects
O
5V tolerant
3.3V LVTTL
PerOE
Peripheral output enable. Used by either the external bus
controller or the DMA controller depending upon the type
of transfer involved. When the NPe405H is the bus master,
it enables the peripherals to drive the bus.
O
5V tolerant
3.3V LVTTL
7
PerR/W
Peripheral read/write. Used when not in external master
mode by either the external bus controller or DMA
controller depending upon the type of transfer involved.
High indicates a read from memory, low indicates a write to
memory.
Otherwise it used by the external master as an input to
indicate the direction of transfer.
I/O
5V tolerant
3.3V LVTTL
1
PerReady
Indicates peripheral is ready to transfer data.
I
5V tolerant
3.3V LVTTL
1
PerBLast
Peripheral burst last. Used to indicate the last transfer of a
memory access.
I/O
5V tolerant
3.3V LVTTL
1, 7
PerClk
Peripheral Clock. Used by an external master and by
synchronous peripheral slaves.
O
5V tolerant
3.3V LVTTL
PerErr
Used to indicate errors from peripherals.
I
5V tolerant
3.3V LVTTL
1, 5
[DMAReq0:3]
DMA request. Used by peripheral slaves to request a data
transfer. Following a system reset, the default mode of the
signals is active-low. They may be programmed to active-
high using the DMA0_POL register.
I
5V tolerant
3.3V LVTTL
1
[DMAAck0:3]
DMA acknowledge. Used to indicate to peripherals that
data transfer is complete. Following a system reset, the
default mode of the signals is active-low. They may be
programmed to active-high using the DMA0_POL register.
O
5V tolerant
3.3V LVTTL
[EOT0:3/TC0:3]
End Of Transfer/Terminal Count. Indication by peripherals
that all data has been transfered, or by DMA controller that
programmed amount of data has been transfered.
Following a system reset, the default mode of the signals is
active-low. They may be programmed to active-high using
the DMA0_POL register.
I/O
5V tolerant
3.3V LVTTL
1
Signal Functional Description (Part 6 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 43.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料
PDF描述
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參數(shù)描述
IBM25NPE405L-3FA133C 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP
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