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| 型號(hào)： | IBM25NPE405H-3BA266CZ |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA580 |
| 封裝： | 35 MM, PLASTIC, EBGA-580 |
| 文件頁數(shù)： | 40/74頁 |
| 文件大小： | 1423K |
| 代理商： | IBM25NPE405H-3BA266CZ |
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Preliminary
PowerNP NPe405H Embedded Processor Data Sheet
45
PCIGnt0[Req]
Gnt0 when internal arbiter is used, or Req when external
arbiter is used
O
5V tolerant
3.3V PCI
PCIGnt1:5
PCIGnt1:5 output when internal arbiter is used.
O
5V tolerant
3.3V PCI
HDLCEX Interface
HDLCEXTxClk
Transmit Clock
I
3.3V LVTTL
HDLCEXTxFS
Transmit Frame Synchronization
I
3.3V LVTTL
HDLCEXTxDataA
Transmit Data port A
O
3.3V LVTTL
HDLCEXTxDataB
Transmit Data port B
O
3.3V LVTTL
HDLCEXRxClk
Receive Clock
I
3.3V LVTTL
HDLCEXRxFS
Receive Frame Synchronization
I
3.3V LVTTL
HDLCEXRxDataA
Receive Data port A
I
3.3V LVTTL
HDLCEXRxDataB
Receive Data port B
I
3.3V LVTTL
[HDLCEXTxEnA]
Transmit Enable port A
O
5V tolerant
3.3V LVTTL
[HDLCEXTxEnB]
Transmit Enable port B
O
5V tolerant
3.3V LVTTL
HDLCMP Interface
HDLCMPTxClk0:3
Transmit Clock signal that controls the transmit bit rate
O
3.3V LVTTL
[HDLCMPTxClk4:7]
Transmit Clock signal that controls the transmit bit rate
O
5V tolerant
3.3V LVTTL
HDLCMPTxData0:3
Transmit Data signal
O
3.3V LVTTL
[HDLCMPTxData4:7]
Transmit Data signal
O
5V tolerant
3.3V LVTTL
[HDLCMPTxEn0:7]
Transmit Data Enable signal that controls when the
external buffer is tri-stated
O
5V tolerant
3.3V LVTTL
HDLCMPRxClk0:3
Receive Clock signal that controls the receive bit rate
I
3.3V LVTTL
[HDLCMPRxClk4:7]
Receive Clock signal that controls the receive bit rate
I
5V tolerant
3.3V LVTTL
HDLCMPRxData0:3
Receive Data signal
I
3.3V LVTTL
[HDLCMPRxData4:7]
Receive Data signal
I
5V tolerant
3.3V LVTTL
Signal Functional Description (Part 2 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 43.
Signal Name
Description
I/O
Type
Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25NPE405H-3DA200CZ | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA580 |
| IBM25NPE405L-3DA200CZ | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| IBM25NPE405L-3FA200CZ | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA324 |
| IBM25NPE405L-3FA266CZ | 32-BIT, 266 MHz, RISC PROCESSOR, PBGA324 |
| IBM25PPC405EP-3GB133CZ | 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25NPE405L-3FA133C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA133CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA200C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA200CZ | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
| IBM25NPE405L-3FA266C | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PowerNP |
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