參數(shù)資料
型號： IBM25NPE405H-3BA266CZ
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, RISC PROCESSOR, PBGA580
封裝： 35 MM, PLASTIC, EBGA-580
文件頁數(shù)： 42/74頁
文件大?。?/td> 1423K
代理商： IBM25NPE405H-3BA266CZ
Preliminary
PowerNP NPe405H Embedded Processor Data Sheet
47
PHY0RxClk
Receiver medium clock. This signal is generated by the
PHY (MII 0).
I
5V tolerant
3.3V LVTTL
1, 4
PHY0RxD0[PHY0Rx0D0][PHY0Rx0D]
PHY0RxD1[PHY0Rx0D1][PHY0Rx1D]
PHY0RxD2[PHY0Rx1D0][PHY0Rx2D]
PHY0RxD3[PHY0Rx1D1][PHY0Rx3D]
Received Data. This is a nibble wide bus from the PHY.
The data is synchronous with PHY0RxClk
(MII 0[RMII 0, 1][SMII 0, 1, 2, 3]).
I
5V tolerant
3.3V LVTTL
1, 4
[PHY1RxD0][PHY1Rx2D0]
[PHY1RxD1][PHY1Rx2D1]
[PHY1RxD2][PHY1Rx3D0]
[PHY1RxD3][PHY1Rx3D1]
Receive Data (MII 1[RMII 2, 3]).
I
5V tolerant
3.3V LVTTL
PHY0RxDV[PHY0CrS1DV]
Receive Data Valid. Data on the Data Bus is valid when
this signal is activated. Deassertion of this signal indicates
end of the frame reception (MII 0).
or
Carrier sense data valid ([RMII 1])
I
5V tolerant
3.3V LVTTL
1, 5
PHY0RxErr[PHY0Rx0Er]
Receive Error. This signal comes from the PHY and is
synchronous with PHY0RxClk (MII 0 [RMII 0]).
I
5V tolerant
3.3V LVTTL
1, 5
PHY0TxClk[PHY0RefClk]
Transmit medium clock. This signal is generated the PHY
([MII 0]).
or
Reference Clock [RMII and SMII].
I
5V tolerant
3.3V LVTTL
1, 4
[PHY1Col][PHY1Rx3Er]
Collision [receive error] signal from the PHY. This is an
asynchronous signal ([MII 1]).
or
Receive Error. This signal comes from the PHY and is
synchronous with PHY1RxClk ([RMII 3]).
I
5V tolerant
3.3V LVTTL
1, 5
[PHY1CrS][PHY1CrS2DV]
Carrier Sense signal from the PHY. This is an
asynchronous signal ([MII 1]).
or
Carrier Sense Data Valid ([RMII 2]).
I
5V tolerant
3.3V LVTTL
[PHY1RxClk]
Receiver medium clock. This signal is generated by the
PHY ([MII 1]).
I
5V tolerant
3.3V LVTTL
1, 4
[PHY1RxDV][PHY1CrS3DV]
Receive Data Valid ([MII 1]).
or
Carrier Sense Data Valid ([RMII 3]).
i
5V tolerant
3.3V LVTTL
[PHY1RxErr][PHY1Rx2Er]
Receive Error. This signal comes from the PHY and is
synchronous with PHY1RxClk ([MII 1][RMII 2]).
I
5V tolerant
3.3V LVTTL
[PHY1TxClk]
Transmit medium clock. This signal is generated the PHY
([MII 1]).
I
5V tolerant
3.3V LVTTL
1, 4
Signal Functional Description (Part 4 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 43 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 43.
Signal Name
Description
I/O
Type
Notes
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