參數(shù)資料
型號(hào)： IBM25PPC405EP-3GB133C
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 133.33 MHz, RISC PROCESSOR, PBGA385
封裝： 31 MM, ENHANCED, PLASTIC, BGA-385
文件頁數(shù)： 28/52頁
文件大?。?/td> 992K
代理商： IBM25PPC405EP-3GB133C
Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Page 34 of 52
6/9/03
PCIReq1:2
PCIReq input when internal arbiter is used.
I
5V tolerant
3.3V PCI
PCIGnt0/Req
Gnt0 when internal arbiter is used
or
Req when external arbiter is used.
O
5V tolerant
3.3V PCI
PCIGnt1:2
PCIGnt output when internal arbiter is used.
O
5V tolerant
3.3V PCI
Ethernet Interface
PHY0Rx0:1D3:0
Received data. This is a nibble wide bus from the PHY. The data
is synchronous with the PHY0RxClk.
I
5V tolerant
3.3V LVTTL
1
EMC0Tx0:1D3:0
Transmit data. A nibble wide data bus towards the net. The data
is synchronous to the PHY0TxClk.
O
5V tolerant
3.3V LVTTL
PHY0Rx0:1Err
Receive Error. This signal comes from the PHY and is
synchronous to the PHY0RxClk.
I
5V tolerant
3.3V LVTTL
1
PHY0Rx0:1Clk
Receive Medium clock. This signal is generated by the PHY.
I
5V tolerant
3.3V LVTTL
1
PHY0Rx0:1DV
Receive Data Valid. Data on the Data Bus is valid when this
signal is activated. Deassertion of this signal indicates end of the
frame reception.
I
5V tolerant
3.3V LVTTL
1
PHY0CrS0:1
Carrier Sense signal from the PHY. This is an asynchronous
signal.
I
5V tolerant
3.3V LVTTL
1
EMC0Tx0:1Err
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous with the
PHYTxClk. It informs the PHY that an error was detected.
O
5V tolerant
3.3V LVTTL
EMC0Tx0:1En
Transmit Enable. This signal is driven by the EMAC to the PHY.
Data is valid during the active state of this signal. Deassertion of
this signal indicates end of frame transmission. This signal is
synchronous to the PHY0TxClk.
O
5V tolerant
3.3V LVTTL
PHY0Tx0:1Clk
This clock comes from the PHY and is the Medium Transmit
clock.
I
5V tolerant
3.3V LVTTL
1
PHY0Col0:1
Collision signal from the PHY. This is an asynchronous signal.
I
5V tolerant
3.3V LVTTL
1
EMC0MDClk
Management Data Clock. The MDClk is sourced to the PHY.
Management information is transferred synchronously with
respect to this clock.
O
5V tolerant
3.3V LVTTL
EMC0MDIO
Management Data Input/Output is a bidirectional signal between
the Ethernet controller and the PHY. It is used to transfer control
and status information.
I/O
5V tolerant
3.3V LVTTL
1
Signal Functional Description (Part 2 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 32.
Signal Name
Description
I/O
Type
Notes
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參數(shù)描述
IBM25PPC405GP3BC200C 制造商:IBM 功能描述:
IBM25PPC405GP-3BC200C 制造商:IBM 功能描述: 制造商:IBM 功能描述:Electronic Component
IBM25PPC405GP-3BD200C 制造商:IBM 功能描述:
IBM25PPC405GP-3BE200C 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|456PIN|PLASTIC
IBM25PPC405GP3BE200CZ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|456PIN|PLASTIC
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