參數(shù)資料
型號: ICS810001DK-21LF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 3/19頁
文件大小: 0K
描述: IC CLK GEN SYNC VCXO DL 32VFQFN
標(biāo)準(zhǔn)包裝: 490
系列: HiPerClockS™, FemtoClock™
類型: 時鐘/頻率發(fā)生器,轉(zhuǎn)換器,抖動衰減器,多路復(fù)用器
PLL:
主要目的: 視頻
輸入: LVCMOS,LVTTL
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 無/無
頻率 - 最大: 175MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-VFQFPN 裸露焊盤(4x4)
包裝: 托盤
其它名稱: 800-2276
ICS810001DK-21LF-ND
ICS810001DK-21 REVISION B APRIL 13, 2010
11
2010 Integrated Device Technology, Inc.
ICS810001-21 Data Sheet
FEMTOCLOCK DUAL VCXO VIDEO PLL
Applications Information
Recommendations for Unused Input Pins
Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k
resistor can be used.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform ance,
power supply isolation is required. The ICS810001-21 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. VDD, VDDA, VDDO and VDDX should be
individually connected to the power supply plane through vias, and
0.01F bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic VDD pin and also shows that VDDA
requires that an additional 10
resistor along with a 10F bypass
capacitor be connected to the VDDA pin.
Figure 1. Power Supply Filtering
VDD
VDDX
VDDA
3.3V
10
10
10F
.01F
10F
.01F
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