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參數(shù)資料
| 型號： | ICS83PR226BKI-01LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER PROGR 10-VFQFPN |
| 標準包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 213.33MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-VQFN 裸露焊盤 |
| 供應商設備封裝： | 10-VFQFPN（5x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 83PR226BKI-01LFT |
ICS83PR226BKI-01 REVISION B AUGUST 10, 2010
6
2010 Integrated Device Technology, Inc.
ICS83PR226I-01 Data Sheet
PROGRAMMABLE FEMTOCLOCK LVPECL OSCILLATOR REPLACEMENT
Table 6B. AC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Please refer to the Phase Noise plots.
NOTE 3: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 106 clock periods.
NOTE 4: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for tREFCLK_HF_RMS
(High Band) and 3.0ps RMS for tREFCLK_LF_RMS (Low Band).
NOTE 5: This parameter is guaranteed using a 25MHz crystal.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fMAX
Output Frequency
83.33
213.33
MHz
tjit(cc)
Cycle-to-Cycle Jitter;
NOTE 1
45
ps
tjit()
RMS Phase Jitter (Random);
NOTE 2
156.25MHz,
Integration Range: 1.875MHz – 20MHz
0.44
ps
125MHz,
Integration Range: 1.875MHz – 20MHz
0.48
ps
100MHz,
Integration Range: 1.875MHz – 20MHz
0.49
ps
tj
(PCIe Gen 1)
Phase Jitter Peak-to-Peak;
NOTE 3
100MHz, (1.2MHz – 21.9MHz),
106 samples,
25MHz crystal input
12.18
ps
125MHz, (1.2MHz – 21.9MHz),
106 samples,
25MHz crystal input
16.41
ps
tREFCLK_HF_RMS
(PCIe Gen 2)
Phase Jitter RMS; NOTE 4
100MHz, 25MHz crystal input
1.47
ps
125MHz, 25MHz crystal input
1.74
ps
tR / tF
Output Rise/Fall Time
20% to 80%
200
700
ps
odc
Output Duty Cycle
47
53
%
tLOCK
PLL Lock Time; NOTE 5
100
ms
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