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參數(shù)資料
| 型號(hào)： | ICS83PR226BKI-01LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER PROGR 10-VFQFPN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | HiPerClockS™, FemtoClock™ |
| 類型： | 時(shí)鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 213.33MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-VQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-VFQFPN（5x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 83PR226BKI-01LFT |
ICS83PR226BKI-01 REVISION B AUGUST 10, 2010
13
2010 Integrated Device Technology, Inc.
ICS83PR226I-01 Data Sheet
PROGRAMMABLE FEMTOCLOCK LVPECL OSCILLATOR REPLACEMENT
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential outputs are low impedance follower outputs that
generate ECL/LVPECL compatible signals. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
3.3V
V
CC - 2V
R1
50
R2
50
RTT
Z
o = 50
Z
o = 50
+
_
RTT =
* Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL
Input
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o = 50
Z
o = 50
LVPECL
Input
3.3V
+
_
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