- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8978 > ICS84021AYLFT (IDT, Integrated Device Technology Inc)IC SYNTHESIZER HIGH FREQ 32-LQFP PDF資料下載
參數(shù)資料
| 型號： | ICS84021AYLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER HIGH FREQ 32-LQFP |
| 標準包裝： | 1,000 |
| 系列： | HiPerClockS™ |
| 類型： | 頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVTTL，晶體 |
| 輸出： | LVCMOS，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 260MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 84021AYLFT |
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ICS84021BY REVISION E AUGUST 18, 2011
2
2011 Integrated Device Technology, Inc.
Functional Description
NOTE: The functional description that follows describes operation
using a 25MHz crystal. Valid PLL loop divider values for different
crystal or input frequencies are defined in the Input Frequency
Characteristics, Table 5, NOTE 1.
The ICS84021 features a fully integrated PLL and therefore requires
no external components for setting the loop bandwidth. A
fundamental crystal is used as the input to the on-chip oscillator. The
output of the oscillator is fed into the phase detector. A 25MHz crystal
provides a 25MHz phase detector reference frequency. The VCO of
the PLL operates over a range of 620MHz to 780MHz. The output of
the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high
or too low), the PLL will not achieve lock. The output of the VCO is
scaled by a divider prior to being sent to each of the LVCMOS output
buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS84021 support two input
modes to program the M divider and N output divider. The two input
operational modes are parallel and serial. Figure 1 shows the timing
diagram for each mode. In parallel mode, the nP_LOAD input is
initially LOW. The data on inputs M0 through M8 and N0 and N1 is
passed directly to the M divider and N output divider. On the
LOW-to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW transition on
nP_LOAD or until a serial event occurs. As a result, the M and N bits
can be hardwired to set the M divider and N output divider to a
specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode.
The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows: fVCO = fxtal x M
The M value and the required values of M0 through M8 are shown in
Table 3B, Programmable VCO Frequency Function Table. Valid M
values for which the PLL will achieve lock for a 25MHz reference are
defined as 25
≤ M ≤ 31. The frequency out is defined as follows:
FOUT = fVCO = fxtal x M
NN
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is
LOW. The shift register is loaded by sampling the S_DATA bits with
the rising edge of S_CLOCK. The contents of the shift register are
loaded into the M divider and N output divider when S_LOAD
transitions from LOW-to-HIGH. The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD. If
S_LOAD is held HIGH, data at the S_DATA input is passed directly to
the M divider and N output divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and test
bits T1 and T0. The internal registers T0 and T1 determine the state
of the TEST output as follows:
Figure 1. Parallel & Serial Load Operations
T1
T0
TEST Output
00
LOW
0
1
S_DATA, Shift Register Input
1
0
Output of M Divider
1
CMOS FOUT
Time
SERIAL LOADING
PARALLEL LOADING
t
S
t
H
t
S
t
H
t
S
M, N
M0
M1
M2
M3
M4
M5
M6
M7
M8
N0
N1
*NULL
T0
T1
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M[0:8], N[0:1]
nP_LOAD
*NOTE: The NULL timing slot must be observed.
相關PDF資料 |
PDF描述 |
|---|---|
| 208494-1 | CONN PLUG CMC HSING 22-3 STD |
| SI5325B-C-GM | IC UP-PROG CLK MULTIPLIER 36-QFN |
| VE-J03-MZ-F2 | CONVERTER MOD DC/DC 24V 25W |
| VE-J03-MZ-F1 | CONVERTER MOD DC/DC 24V 25W |
| 208488-1 | CONN PLUG CMC 16POS STD SER 1 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS84021AYT | 制造商:ICS 制造商全稱:ICS 功能描述:260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER |
| ICS840245AGILF | 功能描述:IC FREQ SYNTHESIZER 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS840245AGILFT | 功能描述:IC FREQ SYNTHESIZER 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:HiPerClockS™, FemtoClock™ 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| ICS84025 | 制造商:ICS 制造商全稱:ICS 功能描述:CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER |
| ICS84025EM | 制造商:ICS 制造商全稱:ICS 功能描述:CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER |
發(fā)布緊急采購，3分鐘左右您將得到回復。