參數(shù)資料
型號(hào): ICS84021AYLFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 13/19頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER HIGH FREQ 32-LQFP
標(biāo)準(zhǔn)包裝: 1,000
系列: HiPerClockS™
類型: 頻率合成器
PLL: 帶旁路
輸入: LVCMOS,LVTTL,晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 260MHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 84021AYLFT
ICS84021 Data Sheet
260MHz, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER
ICS84021BY REVISION E AUGUST 18, 2011
3
2011 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number
Name
Type
Description
1
M5
Input
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD
input. LVCMOS/LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Input
Pulldown
5, 6
N0, N1
Input
Pulldown
Determines N output divider value as defined in Table 3C, Function
Table. LVCMOS/LVTTL interface levels.
7
nc
Unused
No connect.
8, 16
GND
Power
Power supply pins.
9
TEST
Output
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels.
10
VDD
Power
Core supply pin.
11, 12
OE1, OE0
Input
Pullup
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in an Hi-Z state. See Table 3E, OE
Function Table. LVCMOS/LVTTL interface levels.
13
VDDO
Power
Output supply pin.
14, 15
Q1, Q0
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
17
MR
Input
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When Logic LOW, the internal
dividers and the outputs are enabled. Assertion of MR does not affect
loaded M, N, and T values. LVCMOS/LVTTL interface levels.
18
S_CLOCK
Input
Pulldown
Clocks in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
19
S_DATA
Input
Pulldown
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
20
S_LOAD
Input
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS/LVTTL interface levels.
21
VDDA
Power
Analog supply pin.
22
XTAL_SEL
Input
Pullup
Selects between crystal or test inputs as the PLL reference source.
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS/LVTTL interface levels.
23
TEST_CLK
Input
Pulldown
Single-ended test clock input. LVCMOS/LVTTL interface levels.
24,
25
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
26
nP_LOAD
Input
Pulldown
Parallel load input. Determines when data present at M[8:0] is loaded into
M divider, and when data present at N[1:0] sets the N output divider
value. LVCMOS/LVTTL interface levels.
27
VCO_SEL
Input
Pullup
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS/LVTTL interface levels.
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