參數(shù)資料
型號(hào): ICS932S202
英文描述: Frequency Timing Generator for Differential PIIIType Dual-CPU Systems
中文描述: 頻率差分PIIIType雙CPU的系統(tǒng)時(shí)序發(fā)生器
文件頁(yè)數(shù): 2/14頁(yè)
文件大?。?/td> 105K
代理商: ICS932S202
2
ICS932S202
0600A—08/04/03
Pin Descriptions
The
ICS932S202
is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This
chip provides all the clocks required for such a system.
Spread Spectrum may be enabled through I
2
C. Spread spectrum typically reduces system EMI by 8dB to 10dB. This
simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS932S202
employs
a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
General Description
Pin number
1, 7, 13, 19, 25,
31, 36, 41, 45
2
Pin name
Type
Description
GND
PWR
Ground pins
REF0
REF1
SEL24_48
OUT
OUT
IN
14.318MHz reference clock outputs at 3.3V
14.318MHz reference clock outputs at 3.3V
Logic input to select 24 or 48MHz for pin 26 output
4, 10, 16, 23,
28, 35
5
6
VDD
PWR
Power pins 3.3V
X1
X2
PCICLK0
FS0
PCICLK1
FS1
PCICLK2
FS2
PCICLK3
FS3
IN
XTAL_IN 14.318MHz crystal input
XTAL_OUT Crystal output
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
PCI clock output at 3.3V. Synchronous to CPU clocks.
Logic - input for frequency selection
OUT
OUT
IN
OUT
IN
OUT
IN
OUT
IN
22, 21, 20, 18,
17, 15, 14
PCICLK (10:4)
OUT
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
24
PD#
IN
This asynchronous input powers down the chip when drive
active(Low). The internal PLLs are disabled and all the
output clocks are held at a Low state.
24 or 48MHz output selectable by
SEL24_48# (0=48MHz 1=24MHz)
Fixed 48MHz clock output. 3.3V
Logic - input for frequency selection
Clock input of I
2
C input
Data pin for I
2
C circuitry 5V tolerant
3.3V clock outputs. These outputs are stopped when
CPU_STOP# is driven active..
Chipset clock outputs @ 2.5V
CPU clock outputs @ 2.5V.
Power pins for CPUCLKs. 2.5V
IOAPIC clocks @ 2.5V. Synchronous with CPUCLKs.
Power pin for the IOAPIC outputs. 2.5V.
26
24_48MHz
OUT
48MHz
FS4
SCLK
SDATA
OUT/IN
IN
IN
I/O
29
30
34, 33, 32
3V66 (2:0)
OUT
38, 37
40, 42
39, 43
44, 46, 47
48
CPU_CSCLK (1:0)
CPUCLK (1:0)
VDDLCPU
IOAPIC (2:0)
VDDLAPIC
OUT
OUT
PWR
OUT
PWR
27
12
3
8
9
11
相關(guān)PDF資料
PDF描述
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ICS932S208YFLF-T Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS932S203 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Generator with 133MHz Differential CPU Clocks
ICS932S203AF 制造商:INT_CIR_SYS 功能描述:
ICS932S203AFLF 功能描述:IC FREQ GEN W/CPU CLOCK 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP(0.209",5.30mm 寬) 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
ICS932S203AFLFT 功能描述:IC FREQ GEN W/CPU CLOCK 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP(0.209",5.30mm 寬) 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
ICS932S203AFLN 功能描述:IC FREQ GEN W/CPU CLOCK 56-SSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP(0.209",5.30mm 寬) 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT