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參數(shù)資料
| 型號： | ICS9342 |
| 英文描述： | 133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| 中文描述： | 133MHz的時鐘發(fā)生器和集成緩沖器，用于PowerPC的⑩ |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 175K |
| 代理商： | ICS9342 |
ICS9342
Third party brands and names are the property of their respective owners.
Pin Configuration
General Description
The
ICS9342
generates all clocks required for high speed PowerPC RISC microprocessor systems. With a zero delay buffer
chip such as the ICS9112-17 multiple PCI clock outputs can be generated in phase with PCIREF.
Spread Spectrum may be enabled by driving the SS_EN# pin low. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9342
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
PIN NUMBER
1
2,3
4
5
6
7
8
9
10
11
PIN NAME
VDDREF
REF[1:0]
GNDREF
X1
X2
PD#
CPU_STOP#
VDD
GND
PCI_STOP#
TYPE
PWR
OUT
PWR
IN
OUT
IN
IN
PWR
PWR
IN
DESCRIPTION
Ref(1:0), XTAL power supply, nominal 3.3V
14.318 MHz reference clocks
Ground pin for the REF outputs
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Powers down chip, active low.
Stops all CPUCLKs [11:0] at logic 0 level, when input low
3.3V power for the digital core.
Ground pin for the digital core.
Drives PCIREF to logic 0 level, when input low
Spread spectrum is turned on by driving this input low and turned off by
driving it high.
Power supply for PCIREF, nominal 3.3V.
Reference clock for PCI Zero Delay Buffer.
Ground pin for PCIREF.
Frequency select pins.
3.3V power for the Fixed PLL core.
Ground pin for the Fixed PLL core.
3.3V OUT reference clock.
Logic input to select over clocking or under clocking frequencies.
(latched input)
3.3V 1/2 frequency OUT reference clock.
Logic input to select normal or test mode frequencies. (latched input)
Powers down Fixed PLL. When driven to low, OUT and OUT_DIV2 clocks
will be stopped
3.3V power for the PLL core
Frequency select pins for OUT and OUT_DIV2 clocks.
Ground pin for CPU clocks.
3.3V power supply for CPU clocks.
12
SS_EN#
IN
13
14
15
VDDPCI
PCIREF
GNDPCI
FS (2:0)
VDDFP
GNDFP
OUT
PWR
OUT
PWR
IN
PWR
PER
OUT
18, 17, 16
19
20
TEST#
IN
OUT_DIV2
BOOST#
OUT
IN
23
PDFP#
IN
24
VDDA
OUTSEL(1:0)
GNDCPU
VDDCPU
PWR
IN
PWR
PWR
48, 25
26, 31, 36, 41, 46
27, 32, 37, 42, 47
21
22
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICS93701 | DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | DDR Phase Lock Loop Clock Driver |
| ICS93705 | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93705YF-T | DDR Phase Lock Loop Zero Delay Clock Buffer |
| ICS93712YF-PPP-T | 2 DIMM DDR Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9342AFLF | 制造商:Integrated Device Technology Inc 功能描述: |
| ICS9342YF-T | 制造商:ICS 制造商全稱:ICS 功能描述:133MHz Clock Generator and Integrated Buffer for PowerPC⑩ |
| ICS93701 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93701YGT | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Clock Driver |
| ICS93705 | 制造商:ICS 制造商全稱:ICS 功能描述:DDR Phase Lock Loop Zero Delay Clock Buffer |
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