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參數(shù)資料
| 型號： | ICSSSTUB32872A |
| 英文描述： | 28-Bit Registered Buffer for DDR2 |
| 中文描述： | 28位注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 222K |
| 代理商： | ICSSSTUB32872A |
11
1222F—3/13/07
ICSSSTUB32872A
Advance Information
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
V
DD
= 1.8V ± 0.1V
MIN
1
1
MAX
4
4
1
dV/dt_r
dV/dt_f
dV/dt_
Δ
1
V/ns
V/ns
V/ns
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
PARAMETER
UNIT
Electrical Characteristics - DC
T
A
= 0 - 70°C; V
DD
= 2.5 +/-0.2V, V
DDQ
=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
PARAMETERS
V
OH
I
OH
= -8mA
V
OL
I
OL
= 8mA
I
I
All Inputs
V
I
= V
DD
or GND
Standby (Static)
RESET = GND
V
I
= V
IH(AC)
or V
IL(AC)
,
RESET = V
DD
RESET = V
DD
,
V
I
= V
IH(AC)
or V
IL(AC)
,
CLK and CLK switching
50% duty cycle.
RESET = V
DD
,
V
I
= V
IH(AC)
or V
IL (AC)
,
CLK and CLK switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
Data Inputs
CLK and CLK
RESET
Notes:
1 - Guaranteed by design, not 100% tested in production.
V
DDQ
1.7V
1.7V
1.9V
MIN
1.2
TYP
MAX
UNITS
0.5
±5
200
μA
μA
Operating (Static)
150
mA
Dynamic operating
(clock only)
TBD
μA/clock
MHz
Dynamic Operating
(per each data
input)
TBD
μA/ clock
MHz/data
2.5
2
5
3.8
4.5
pF
C
i
V
I
= V
DDQ
or GND
I
DD
I
DDD
I
O
= 0
CONDITIONS
V
I
= V
REF
±350mV
V
ICR
= 1.25V, V
I(PP)
= 360mV
pF
V
1.8V
1.9V
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