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參數(shù)資料
| 型號： | ICSSSTUB32872A |
| 英文描述： | 28-Bit Registered Buffer for DDR2 |
| 中文描述： | 28位注冊緩沖DDR2內(nèi)存 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 222K |
| 代理商： | ICSSSTUB32872A |
15
1222F—3/13/07
ICSSSTUB32872A
Advance Information
3 Test circuits and switching waveforms (cont’d)
3.3 Error output load circuit and voltage measurement information (V
DD
= 1.8 V ± 0.1 V)
All input pulses are supplied by generators having the following characteristics: PRR
Z
o
= 50
; input slew rate = 1 V/ns ± 20%, unless otherwise specified.
Ω
10 MHz;
(1) C
L
includes probe and jig capacitance.
Figure 28 — Load circuit, error output measurements
—
—
—
C
= 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Test Point
DUT
Out
R
L
= 1K
V
DD
LVCMOS
RST
Input
PLH
t
Output
Waveform 2
CC
V
/2
0.15 V
CC
V
0 V
OH
V
0 V
Figure 29
Voltage waveforms, open-drain output low-to-high transition time with respect to reset input
Timing
Inputs
Output
Waveform 1
PHL
t
ICR
V
CC
V
/2
ICR
V
VI(PP)
CC
V
OL
V
Timing
Inputs
Output
Waveform 2
PHL
t
ICR
V
ICR
V
VI(PP)
OH
V
V
0
0.15 V
Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs
Figure 30
Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs
Figure 31
_ _ _ _ _ _ _ _ _ _ _
_ _ _ _ _ _ _ _ _ _ _
Ω
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