參數(shù)資料
型號： ICSSSTUBF32866Az(LF)T
英文描述： 25-Bit Configurable Registered Buffer for DDR2
中文描述： 25位可配置的注冊緩沖DDR2內(nèi)存
文件頁數(shù)： 17/28頁
文件大?。?/td> 308K
代理商： ICSSSTUBF32866AZ(LF)T
17
ICSSSTUBF32866A
Advance Information
1240—07/17/06
2. Device standard (cont'd)
PAR_IN is driven from PPO of the first SSTU32866 device
If the data is clocked in on the n clock pulse, the QERR# output signal will be generated on the n+2 clock pulse, and it will be valid on
the n+3 clock pulse. If an erro occurs and the QERR# output is driven low, it stays latched low for a minimum of two clock cycles or
until RST# is driven low.
CK
D1D14
RST#
tsu
tpd
CK to PPO
th
tsu
th
tpdm, tpdmss
CK to Q
DCS#
CSR#
CK#
Q1Q14
PAR_IN
n
n + 1
n + 2
PPO
n + 3
n + 4
QERR#
(not used)
tPHL or tPLH
CK to QERR#
Unknown input
event
H or L
Output signal is dependent on
the prior unknown input event
Data to QERR#
Latency
Data to PPO
Latency
Figure 16 — Timing diagram for the second SSTU32866 (1:2 register-B cofiguration) device used in
pair; C0=1, C1=1; RST# being held high
相關(guān)PDF資料
PDF描述
ICSSSTUF32864A 25-Bit Configurable Registered Buffer for DDR2
ICSSSTUF32864AYHLF-T 25-Bit Configurable Registered Buffer for DDR2
ICSSSTV16857CG-T DDR 14-Bit Registered Buffer
ICSSSTV16857yG-T DDR 14-Bit Registered Buffer
ICSSSTV16859CG-T DDR 13-Bit to 26-Bit Registered Buffer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICSSSTUF32864A 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2
ICSSSTUF32864AYHLF-T 制造商:ICS 制造商全稱:ICS 功能描述:25-Bit Configurable Registered Buffer for DDR2
ICSSSTV16857 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer
ICSSSTV16857CG-T 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer
ICSSSTV16857YG-T 制造商:ICS 制造商全稱:ICS 功能描述:DDR 14-Bit Registered Buffer
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