參數(shù)資料
型號: IDT5V9351PRI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: LOW VOLTAGE PLL CLOCK DRIVER
中文描述: PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: TQFP-32
文件頁數(shù): 2/10頁
文件大?。?/td> 85K
代理商: IDT5V9351PRI
INDUSTRIAL TEMPERATURE RANGE
2
IDT5V9351
LOW VOLTAGE PLL CLOCK DRIVER
TQFP
TOP VIEW
PIN CONFIGURATION
G
Q
B
V
C
Q
A
T
P
R
G
V
C
Q
D
Q
D
G
Q
D
V
C
O
P
VCCA
f
SELA
f
SELB
f
SELC
FBIN
GND
PECL_CLK
Q
C0
V
CC
Q
C1
GND
Q
D0
V
CC
Q
D1
GND
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
f
SELD
Symbol
V
CC
V
I
V
O
I
IN
I
O
T
STG
Description
Max.
Unit
V
V
V
mA
mA
°C
Supply Voltage
Input Voltage
DC Output Voltage
Input Current
DC Output Current
Storage Temperature
–0.3 to +4.6
–0.3 to V
CC
+0.3
–0.3 to V
CC
+0.3
±20
±50
–55 to +150
ABSOLUTE MAX IMUM RATINGS
(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
NOTES:
1. IDT5V9351 requires an external RC filter for the analog power supply pin V
CCA
.
2. For V
CC
= 2.5V, R
F
= 9-10
, C
F
= 22
μ
F.
For V
CC
= 3.3V, R
F
= 5-15
, C
F
= 22
μ
F.
LOGIC DIAGRAM
(1,2)
R
F
V
CC
C
F
V
CCA
V
CC
10nF
33...100nF
Symbol
C
IN
Parameter
Input Capacitance
Min.
Typ.
4
Max.
Unit
pF
C
PD
Power Dissipation
Capacitance
10
pF
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
V
TT
HBM
LU
Description
Output Termnation Voltage
ESD (Human Body Model)
Latch-Up Immunity
Min.
Typ.
V
CC
/2
Max.
Unit
V
V
mA
2000
200
GENERAL SPECIFICATIONS
相關(guān)PDF資料
PDF描述
IDT5V9351 LOW VOLTAGE PLL CLOCK DRIVER
IDT5V9351PR LOW VOLTAGE PLL CLOCK DRIVER
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IDT5V9352PRI 3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
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