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參數(shù)資料
| 型號： | IDT7130SA35FG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM |
| 中文描述： | 1K X 8 DUAL-PORT SRAM, 35 ns, CQFP48 |
| 封裝： | 0.750 X 0.750 INCH, 0.110 INCH HEIGHT, GREEN, CERAMIC, QFP-48 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 167K |
| 代理商： | IDT7130SA35FG |
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
16
Truth Table I — Non-Contention Read/Write Control
(4)
Inputs
(1)
Truth Tables
Truth Table II — Interrupt Flag
(1,4)
Truth Table III — Address
BUSY
Arbitration
Inputs
NOTES:
1. Pins
BUSY
L
and
BUSY
R
are both outputs for IDT7130 (master). Both are inputs for
IDT7140 (slave).
BUSY
X
outputs on the IDT7130 are open drain, not push-pull
outputs. On slaves the
BUSY
X
input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If t
APS
is not met, either
BUSY
L
or
BUSY
R
= LOW will
result.
BUSY
L
and
BUSY
R
outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when
BUSY
L
outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when
BUSY
R
outputs are driving LOW regardless of actual logic level on
the pin.
NOTES:
1. A
0L
– A
10L
A
0R
– A
10R
.
2. If
BUSY
= L, data is not written.
3. If
BUSY
= L, data may not be valid, see t
WDD
and t
DDD
timng.
4. 'H' = V
IH
, 'L' = V
IL
, 'X' = DONT CARE, 'Z' = HIGH IMPEDANCE
NOTES
:
1. Assumes
BUSY
L
=
BUSY
R
= V
IH
2. If
BUSY
L
= V
IL
, then No Change.
3. If
BUSY
R
= V
IL
, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DONT CARE
Function
R/
W
CE
OE
D
0-7
X
H
X
Z
Port Disabled and in Power-Down Mode, I
SB2
or I
SB4
X
H
X
Z
CE
R
=
CE
L
= V
IH
, Power-Down Mode, I
SB1
or I
SB3
L
L
X
DATA
IN
Data on Port Written into Memory
(2)
H
L
L
DATA
OUT
Data in Memory Output on Port
(3)
H
L
H
Z
High Impedance Outputs
2689 tbl 13
Left Port
Right Port
Function
R/
W
L
CE
L
OE
L
A
9L
-A
0L
INT
L
R/
W
R
CE
R
OE
R
A
9R
-A
0R
INT
R
L
L
X
3FF
X
X
X
X
X
L
(2)
Set Right
INT
R
Flag
X
X
X
X
X
X
L
L
3FF
H
(3)
Reset Right
INT
R
Flag
X
X
X
X
L
(3)
L
L
X
3FE
X
Set Left
INT
L
Flag
X
L
L
3FE
H
(2)
X
X
X
X
X
Reset Left
INT
L
Flag
2689 tbl 14
Outputs
Function
CE
L
CE
R
A
0L
-A
9L
A
0R
-A
9R
BUSY
L
(1)
BUSY
R
(1)
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit
(3)
2689 tbl 15
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