參數(shù)資料
型號(hào): IDT7130SA35FG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
中文描述: 1K X 8 DUAL-PORT SRAM, 35 ns, CQFP48
封裝: 0.750 X 0.750 INCH, 0.110 INCH HEIGHT, GREEN, CERAMIC, QFP-48
文件頁數(shù): 9/19頁
文件大?。?/td> 167K
代理商: IDT7130SA35FG
9
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
T iming Waveform of Read Cycle No. 1, Either S ide
(1)
T iming Waveform of Read Cycle No. 2, Either S ide
(3)
NOTES:
1. Timng depends on which signal is asserted last,
OE
or
CE
.
2. Timng depends on which signal is deaserted first,
OE
or
CE
.
3. R/
W
= V
IH
and
OE
= V
IL
, and the address is valid prior to or coincidental with
CE
transition LOW.
4.
Start of valid data depends on which timng becomes effective last t
AOE
, t
ACE
,
t
AA
, and
t
BDD
.
ADDRESS
DATA
OUT
t
RC
t
OH
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
2689 drw 08
t
BDDH
(2,3)
BUSY
OUT
NOTES:
1. R/
W
= V
IH
,
CE
= V
IL
, and is
OE
= V
IL
. Address is valid prior to the coincidental with
CE
transition LOW.
2. t
BDD
delay is required only in the case where the opposite port is completing a write operation to the same the address location. For simultaneous read operations,
BUSY
has no relationship to valid output data.
3. Start of valid data depends on which timng becomes effective last t
AOE
, t
ACE
, t
AA
, and t
BDD
.
CE
t
ACE
t
AOE
t
HZ
t
LZ
t
PD
VALID DATA
t
PU
50%
OE
DATA
OUT
CURRENT
I
CC
I
SS
50%
2689 drw 09
(4)
(1)
(1)
(2)
(2)
(4)
t
LZ
t
HZ
相關(guān)PDF資料
PDF描述
IDT7130SA35FGB HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
IDT7130SA35FGI HIGH SPEED 1K X 8 DUAL-PORT STATIC SRAM
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