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參數(shù)資料
| 型號(hào)： | IDT723626L12PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 256X36X2 128QFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲(chǔ)容量： | 18.4K（256 x 36 x 2） |
| 數(shù)據(jù)速率： | 83MHz |
| 訪問時(shí)間： | 12ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723626L12PF8 |
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11
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
SPM
FS1/
SEN
FS0/SD
MRS1
MRS2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
HH
H
↑
X64
X
HH
H
↑↑
64
HH
L
↑
X16
X
HH
L
↑↑
16
HL
H
↑
X8
X
HL
H
↑↑
88
HL
L
↑↑
Parallel programming via Port A
LH
L
↑↑
Serial programming via SD
LH
H
↑↑
Reserved
LL
H
↑↑
Reserved
LL
L
↑↑
Reserved
outputs, no read request necessary. Subsequent words must be accessed by
performing a formal read operation. Refer to Figure 4 (FIFO1 Master Reset)
and Figure 5 (FIFO2 Master Reset) for First Word Fall Through select timing
diagrams.
Following Master Reset, the level applied to the BE/
FWFTinputtochoose
the desired timing mode must remain static throughout FIFO operation.
PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS
Four registers in these FIFOs are used to hold the offset values for the
Almost-EmptyandAlmost-Fullflags.ThePortBAlmost-Emptyflag(
AEB)Offset
register is labeled X1 and the Port A Almost-Empty flag (
AEA)Offsetregisteris
labeled X2. The Port A Almost-Full flag (
AFA)OffsetregisterislabeledY1and
thePortCAlmost-Fullflag(
AFC)OffsetregisterislabeledY2.Theindexofeach
register name corresponds to its FIFO number. The Offset registers can be
loaded with preset values during the reset of a FIFO, programmed in parallel
using the FIFO’s Port A data inputs, or programmed in serial using the Serial
Data (SD) input (see Table 1).
SPM,FS0/SD,andFS1/SENfunctionthesamewayinbothIDTStandard
and FWFT modes.
PRESET VALUES
To load a FIFO’s Almost-Empty flag and Almost-Full flag Offset registers
with one of the three preset values listed in Table 1, the Serial Program Mode
(
SPM) and at least one of the flag-select inputs must be HIGH during the LOW-
to-HIGH transition of its Master Reset (
MRS1 and MRS2) input. For example, to
load the preset value of 64 into X1 and Y1,
SPM, FS0 and FS1 must be HIGH
when FlFO1 reset (
MRS1) returns HIGH. Flag Offset registers associated with
FIFO2 are loaded with one of the preset values in the same way with FIFO2
Master Reset (
MRS2)toggledsimultaneouslywithFIFO1MasterReset(MRS1).
For relevant Preset value loading timing diagrams, see Figure 4 and 5.
PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from Port A, perform a Master
Reset on both FlFOs simultaneously with
SPMHIGHandFS0andFS1LOW
during the LOW-to-HIGH transition of
MRS1 and MRS2. After this reset is
complete,thefirstfourwritestoFIFO1donotstoredatainRAMbutloadtheOffset
registers in the order Y1, X1, Y2, X2. The Port A data inputs used by the Offset
registers are (A7-A0), (A8-A0), or (A9-A0) for the IDT723626, IDT723636,
or IDT723646, respectively. The highest numbered input is used as the most
significant bit of the binary number in each case. Valid programming values for
theregistersrangefrom1to252fortheIDT723626;1to508fortheIDT723636;
and1to1,020fortheIDT723646.AfteralltheOffsetregistersareprogrammed
from Port A, the Port C Full/Input Ready flag (
FFC/IRC)issetHIGH,andboth
FIFOs begin normal operation.
Refer to Figure 8 for a timing diagram illustration for parallel programming
of the flag offset values.
SERIAL LOAD
To program the X1, X2, Y1, and Y2 registers serially, initiate a Master
Reset with
SPMLOW,FS0/SDLOWandFS1/SENHIGHduringtheLOW-to-
HIGH transition of
MRS1 and MRS2. After this reset is complete, the X and Y
register values are loaded bit-wise through the FS0/SD input on each LOW-
to-HIGH transition of CLKA that the FS1/
SENinputisLOW.Thereare32-,36-
, or 40-bit writes needed to complete the programming for the IDT723626,
IDT723636, or IDT723646, respectively. The four registers are written in the
order Y1, X1, Y2 and finally, X2. The first-bit write stores the most significant bit
of the Y1 register and the last-bit write stores the least significant bit of the X2
register. Each register value can be programmed from 1 to 252 (IDT723626),
1 to 508 (IDT723636), or 1 to 1,020 (IDT723646).
When the option to program the Offset registers serially is chosen, the Port
AFull/InputReady(
FFA/IRA)flagremainsLOWuntilallregisterbitsarewritten.
FFA/IRAissetHIGHbytheLOW-to-HIGHtransitionofCLKAafterthelastbit
is loaded to allow normal FIFO1 operation. The Port B Full/Input Ready (
FFC/
IRC) flag also remains LOW throughout the serial programming process, until
allregisterbitsarewritten.
FFC/IRCissetHIGHbytheLOW-to-HIGHtransition
of CLKC after the last bit is loaded to allow normal FIFO2 operation.
See Figure 9 timing diagram, Serial Programming of the Almost-Full Flag
and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT
Modes).
NOTES:
1. X1 register holds the offset for
AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for
AEA; Y2 register holds the offset for AFC.
TABLE 1 — FLAG PROGRAMMING
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參數(shù)描述 |
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| IDT723626L15PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L15PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723631L15PF | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723631L15PF8 | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723631L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 512X36 120-TQFP |
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