參數(shù)資料
型號: IDT723626L12PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 34/35頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 256X36X2 128QFP
標準包裝: 1,000
系列: 7200
功能: 同步
存儲容量: 18.4K(256 x 36 x 2)
數(shù)據(jù)速率: 83MHz
訪問時間: 12ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723626L12PF8
8
COMMERCIAL TEMPERATURE RANGE
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLT-
AGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V ±10%, TA = 0
°C to +70°C)
Commercial
IDT723626L12
IDT723626L15
IDT723636L12
IDT723636L15
IDT723646L12
IDT723646L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
fS
Clock Frequency, CLKA, CLKB, or CLKC
83
66.7
MHz
tCLK
Clock Cycle Time, CLKA, CLKB, or CLKC
12
15
ns
tCLKH
Pulse Duration, CLKA, CLKB, or CLKC HIGH
5
6
ns
tCLKL
Pulse Duration, CLKA, CLKB, OR CLKC LOW
5
6
ns
tDS
Setup Time, A0-A35 before CLKA
↑ and C0-C17 before CLKC↑
3—
4
ns
tENS1
Setup Time,
CSA and W/RA before CLKA
↑; CSB before CLKB↑
4
4.5
ns
tENS2
Setup Time, ENA and MBA before CLKA
↑; RENB and MBB before CLKB↑ ;
3
4.5
ns
WENC and MBC before CLKC
tRSTS
Setup Time,
MRS1, MRS2, PRS1, or PRS2 LOW before CLKA
↑ or CLKB↑(2)
5—
5
ns
tFSS
Setup Time, FS0 and FS1 before
MRS1 and MRS2 HIGH
7.5
7.5
ns
tBES
Setup Time, BE/
FWFT before MRS1 and MRS2 HIGH
7.5
7.5
ns
tSPMS
Setup Time,
SPM before MRS1 and MRS2 HIGH
7.5
7.5
ns
tSDS
Setup Time, FS0/SD before CLKA
3—
4
ns
tSENS
Setup Time, FS1/
SEN before CLKA
3—
4
ns
tFWS
Setup Time, BE/
FWFTbefore CLKA
0—
0
ns
tDH
Hold Time, A0-A35 after CLKA
↑ and C0-C17 after CLKC↑
0.5
1
ns
tENH
Hold Time,
CSA, W/RA, ENA, and MBA after CLKA
↑; CSB, RENB, and MBB
0.5
1
ns
after CLKB
↑;WENCandMBCafterCLKC↑
tRSTH
Hold Time,
MRS1, MRS2, PRS1 or PRS2 LOW after CLKA
↑ or CLKB↑(2)
4—
4
ns
tFSH
Hold Time, FS0 and FS1 after
MRS1 and MRS2 HIGH
2
2
ns
tBEH
Hold Time, BE/
FWFT after MRS1 and MRS2 HIGH
2
2
ns
tSPMH
Hold Time,
SPM after MRS1 and MRS2 HIGH
2
2
ns
tSDH
Hold Time, FS0/SD after CLKA
0.5
1
ns
tSENH
Hold Time, FS1/
SEN HIGH after CLKA
0.5
1
ns
tSPH
Hold Time, FS1/
SEN HIGH after MRS1 and MRS2 HIGH
2
2
ns
tSKEW1(3)
Skew Time, between CLKA
↑and CLKB↑ for EFB/ORB and FFA/IRA; between
5
7.5
ns
CLKA
↑ and CLKC↑ for EFA/ORA and FFC/IRC
tSKEW2(3,4)
Skew Time, between CLKA
↑ andCLKB↑ forAEBandAFA;between CLKA↑ and
12
12
ns
CLKC
↑ for AEA and AFC
NOTES:
1. Industrial temperature range product is available by special order.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.
4. Design simulated, not tested (typical values).
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