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參數(shù)資料
| 型號： | IDT723626L12PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 4/35頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 256X36X2 128QFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲容量： | 18.4K（256 x 36 x 2） |
| 數(shù)據(jù)速率： | 83MHz |
| 訪問時間： | 12ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723626L12PF8 |
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12
COMMERCIAL TEMPERATURE RANGE
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
CSA
W/
RA
ENA
MBA
CLKA
DATA A (A0-A35) I/O
PORT FUNCTION
H
X
High-Impedance
None
L
H
L
X
Input
None
LH
H
L
↑
Input
FIFO1 write
LH
H
↑
Input
Mail1 write
L
X
Output
None
LL
H
L
↑
Output
FIFO2 read
L
H
X
Output
None
LL
H
↑
Output
Mail2 read (set
MBF2 HIGH)
CSB
RENB
MBB
CLKB
DATA B (B0-B17) OUTPUTS
PORT FUNCTION
H
X
High-Impedance
None
L
X
Output
None
LH
L
↑
Output
FIFO1 read
L
H
X
Output
None
LH
H
↑
Output
Mail1 read (set
MBF1 HIGH)
TABLE 4 — PORT C ENABLE FUNCTION TABLE
TABLE 3 — PORT B ENABLE FUNCTION TABLE
WENC
MBC
CLKC
DATA C (C0-C17) INPUTS
PORT FUNCTION
HL
↑
Input
FIFO2 write
HH
↑
Input
Mail2 write
L
X
Input
None
L
H
X
Input
None
FIFO WRITE/READ OPERATION
The state of the Port A data (A0-A35) outputs is controlled by Port A Chip
Select (
CSA)andPortAWrite/ReadSelect(W/RA).TheA0-A35outputsare
in the High-impedance state when either
CSA or W/RAisHIGH.TheA0-A35
outputs are active when both
CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is
LOW, and
FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when
CSAisLOW,W/RAisLOW,ENA
is HIGH, MBA is LOW, and
EFA/ORAisHIGH(seeTable2).FIFOreadsand
writesonPortAareindependentofanyconcurrentPortBandPortCoperation.
ThestateofthePortBdata(B0-B17)outputsiscontrolledbythePortBChip
Select(
CSB).TheB0-B17outputsareinthehigh-impedancestatewhenCSB
is HIGH. The B0-B17 outputs are active when
CSB is LOW.
DataisreadfromFIFO1totheB0-B17outputsbyaLOW-to-HIGHtransition
of CLKB when
CSB is LOW, RENB is HIGH, MBB is LOW and EFB/ORB is
HIGH (see Table 3). FIFO reads on Port B are independent of any concurrent
Port A and Port C operations.
Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH
transition of CLKC when WENB is HIGH, MBC is LOW, and
FFC/IRC is HIGH
(see Table 4). FIFO writes on Port C are independent of any concurrent Port A
and Port B operation.
Thesetupandholdtimeconstraintsfor
CSAandW/RAwithregardtoCLKA
as well as
CSB with regard to CLKB are only for enabling write and read
operations and are not related to high-impedance control of the data outputs.
If ENA is LOW during a clock cycle, either
CSA or W/RA may change states
during the setup and hold time window of the cycle. This is also true for
CSB
when RENB is LOW.
When operating the FIFO in FWFT mode and the Output Ready flag is
LOW, the next word written is automatically sent to the FIFO’s output register
bytheLOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflag
HIGH.WhentheOutputReadyflagisHIGH,subsequentdataisclockedtothe
outputregistersonlywhenareadisselectedusing
CSA,W/RA,ENAandMBA
at Port A or using
CSB, RENB and MBB at Port B.
When operating the FIFO in IDT Standard mode, the first word will cause
the Empty Flag to change state on the second LOW-to-HIGH transition of
thereadclock.Thedatawordwillnotbeautomaticallysenttotheoutputregister.
Instead, data residing in the FIFO’s memory array is clocked to the output
register only when a read is selected using
CSA W/RA ENA and MBA at Port
A or using
CSB, RENB and MBB at Port B. Relevant write and read timing
diagrams for Port A can be found in Figure 10 and 15. Relevant read and write
timing diagrams for Port B and Port C, together with Bus-Matching and Endian
Select operations can be found in Figures 11 to 14.
TABLE 2 — PORT A ENABLE FUNCTION TABLE
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| IDT723626L15PF | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723626L15PF8 | 功能描述:IC FIFO SYNC 256X36X2 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723631L15PF | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723631L15PF8 | 功能描述:IC FIFO SYNC 512X36 120-TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT723631L15PFG | 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SYNC 512X36 120-TQFP |
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