參數(shù)資料
型號(hào): IDT723643L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 22/28頁
文件大?。?/td> 0K
描述: IC FIFO SYNC 1024X36 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲(chǔ)容量: 36.8K(1K x 36)
數(shù)據(jù)速率: 67MHz
訪問時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 723643L15PF8
3
COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
is useful since it permits flushing of the FIFO memory without changing any
configurationsettings.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstword
written to an empty FIFO appears automatically on the outputs, no read
operation required (Nevertheless, accessing subsequent words does neces-
sitate a formal read request). The state of the BE/
FWFT pin during Reset
determines the mode in use.
The FIFO has a combined Empty/Output Ready Flag (
EF/OR ) and a
combinedFull/InputReadyFlag(
FF/IR). TheEFandFFfunctionsareselected
in the IDT Standard mode.
EF indicates whether or not the FIFO memory is
empty.
FF shows whether the memory is full or not. The IR and OR functions
are selected in the First Word Fall Through mode. IR indicates whether or not
theFIFOhasavailablememorylocations.ORshowswhethertheFIFOhasdata
available for reading or not. It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost-Empty flag (
AE)andaprogram-
mable Almost-Full flag (
AF). AE indicates when a selected number of words
remainin theFIFOmemoryachieveapredetermined"almost-emptystate".
AF
indicates when the FIFO contains more than a selected number of words.
FF/IRandAFaretwo-stagesynchronizedtotheportclockthatwritesdata
into its array.
EF/ORandAEaretwo-stagesynchronizedtotheportclockthat
reads data from its array. Programmable offsets for
AE andAF areloaded in
parallelusingPortAorinserialviatheSDinput.TheSerialProgrammingMode
pin(
SPM)makesthisselection.Threedefaultoffsetsettingsarealsoprovided.
The
AE thresholdcanbesetat8,16or64locationsfromtheemptyboundary
and the
AFthresholdcanbesetat8,16or64locationsfromthefullboundary.
All these choices are made using the FS0 and FS1 inputs during Reset.
Two or more devices may be used in parallel to create wider data paths.
In First Word Fall Through mode, more than one device may be connected in
series to create greater word depths. The addition of external components is
unnecessary.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum. Initiatinganyoperation(byactivatingcontrol
inputs) will immediately take the device out of the Power Down state.
The IDT723623/723633/723643 are characterized for operation from 0
°C
to 70
°C.Industrialtemperaturerange(-40°C to+85°C)isavailablebyspecial
order. They are fabricated using IDT’s high speed, submicron CMOS
technology.
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