- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9996 > IDT723643L15PF8 (IDT, Integrated Device Technology Inc)IC FIFO SYNC 1024X36 128QFP PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT723643L15PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FIFO SYNC 1024X36 128QFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 7200 |
| 功能： | 同步 |
| 存儲(chǔ)容量： | 36.8K（1K x 36） |
| 數(shù)據(jù)速率： | 67MHz |
| 訪問時(shí)間： | 15ns |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 723643L15PF8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁
4
COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bit bidirectional data port for side A.
AE
Almost-Empty
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in the FIFO
Flag (Port B)
is less than or equal to the value in the Almost-Empty B offset register, X.
AF
Almost-Full
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in the
Flag (Port A)
FIFO is less than or equal to the value in the Almost-Full A offset register, Y.
B0-B35
Port B Data
I/O
36-bit bidirectional data port for side B.
BE/
FWFT
Big-Endian/
I
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this case,
First Word
depending on the bus size, the most significant byte or word written to Port A is read from Port B first. A
Fall Through
LOW on BE will select Little-Endian operation. In this case, the least significant byte or word written to Port A
is read from Port B first. After Master Reset, this pin selects the timing mode. A HIGH on
FWFT selects IDT
Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the
level on
FWFT must be static throughout device operation.
BM(1)
Bus-Match
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A
Select (Port B)
LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian
arrangement for Port B. The level of BM must be static throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or
coincident to CLKB.
FF/IR and AF are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or
coincident to CLKA.
EF/OR and AE are synchronized to the LOW-to-HIGH transition of CLKB.
CSA
Port A Chip
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
Select
outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write on Port B. The B0-B35
Select
outputs are in the high-impedance state when
CSB is HIGH.
EF/OR
Empty/Output
O
This is a dual function pin. In the IDT Standard mode, the
EF function is selected. EF indicates whether or
Ready Flag
not the FIFO memory is empty. In the FWFT mode, the OR function is selected. OR indicates the presence of valid
(Port B)
dataontheB0-B35outputs,availableforreading.
EF/ORissynchronizedtotheLOW-to-HIGHtransitionofCLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
FF/IR
Full/Input
O
This is a dual function pin. In the IDT Standard mode, the
FF function is selected. FF indicates whether or
Ready Flag
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there
(Port A)
is space available for writing to the FIFO memory.
FF/IR is synchronized to the LOW-to-HIGH transition of
CLKA.
FS1/
SEN
FlagOffset
I
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Reset,
Select 1/
FS1/
SENandFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.Threeoffsetregister
Serial Enable,
programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel
load from Port A, and serial load.
FS0/SD
FlagOffset
I
When serial load is selected for flag offset register programming, FS1/
SEN is used as an enable synchronous
Select 0/
to the LOW-to-HIGH transition of CLKA. When FS1/
SEN is LOW, a rising edge on CLKA load the bit present
Serial Data
on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 16
for the IDT723623, 18 for the IDT723633, and 20 for the IDT723643. The first bit write stores the Y-register
MSB and the last bit write stores the X-register LSB.
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
Select
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
Select
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level
selects FIFO data for output.
MBF1
Mail1 Register
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to
Flag
the mail1 register are inhibited while
MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB
when a Port B read is selected and MBB is HIGH.
MBF1 is set HIGH following either a Reset (RS1) or Partial
Reset (
PRS).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT83SL38IB | IC LIU SH T1/E1/J1 OCTAL 225BGA |
| MS27472T10B35SC | CONN RCPT 13POS WALL MNT W/SCKT |
| XRT75R03IVTR-F | IC LIU E3/DS3/STS-1 3CH 128LQFP |
| VE-21W-MX-F4 | CONVERTER MOD DC/DC 5.5V 75W |
| XRT75R03IVTR | IC LIU E3/DS3/STS-1 3CH 128LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT723644L12PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723644L12PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723644L15PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723644L15PF8 | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT723646L12PF | 功能描述:IC FIFO SYNC 2048X36 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:7200 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。