參數(shù)資料
型號(hào): IDT723643L15PF8
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 3/28頁(yè)
文件大?。?/td> 0K
描述: IC FIFO SYNC 1024X36 128QFP
標(biāo)準(zhǔn)包裝: 1,000
系列: 7200
功能: 同步
存儲(chǔ)容量: 36.8K(1K x 36)
數(shù)據(jù)速率: 67MHz
訪問(wèn)時(shí)間: 15ns
電源電壓: 4.5 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱(chēng): 723643L15PF8
11
COMMERCIALTEMPERATURERANGE
IDT723623/723633/723643 BUS-MATCHING SyncFIFO
256 x 36, 512 x 36, 1,024 x 36
TABLE 1 — FLAG PROGRAMMING
SPM
FS1/
SEN
FSO/SD
RS1
X AND Y REGlSTERS(1)
HH
H
64
HH
L
16
HL
H
8
HL
L
Parallel programming via Port A
LH
L
Serial Programming via SD
LH
H
reserved
LL
H
reserved
LL
L
reserved
NOTE:
1. X register holds the offset for
AE; Y register holds the offset for AF.
— PARALLEL LOAD FROM PORT A
To program the X and Y registers from Port A, perform a Reset on with
SPMHIGHandFS0andFS1LOWduringtheLOW-to-HIGHtransitionofRS1.
After this reset is complete, the first two writes to the FIFO do not store data in
RAM. The first two write cycles load the offset registers in the order Y, X. On
thethirdwritecycletheFIFOisreadytobeloadedwithadataword. SeeFigure
5, Parallel Programming of the Almost-Full Flag and Almost-Empty Flag
Offset Values after Reset (IDT Standard and FWFT modes), for a detailed
timingdiagram.ThePortAdatainputsusedbytheoffsetregistersare(A7-A0),
(A8-A0), or (A9-A0) for the IDT723623, IDT723633 or IDT723643, respec-
tively. Thehighestnumberedinputisusedasthemostsignificantbitofthebinary
number in each case. Valid programming values for the registers range from
1 to 252 for the IDT723623; 1 to 508 for the IDT723633; and 1 to 1,020 for the
IDT723643. After all the offset registers are programmed from Port A the FIFO
begins normal operation.
— SERIAL LOAD
To program the X and Y registers serially, initiate a Reset with
SPMLOW,
FS0/SDLOWandFS1/
SENHIGHduringtheLOW-to-HIGHtransitionofRS1.
After this reset is complete, the X and Y register values are loaded bit-wise
through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the
FS1/
SEN input is LOW. There are 16-, 18- or 20-bit writes are needed to
complete the programming for the IDT723623, IDT723633, or IDT723643,
respectively. ThetworegistersarewrittenintheorderY,X.Eachregistervalue
CSA
W/
RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
PORT FUNCTION
H
X
High-Impedance
None
L
H
L
X
Input
None
LH
H
L
Input
FIFO write
LH
H
Input
Mail1 write
L
X
Output
None
LL
H
L
Output
None
L
H
X
Output
None
LL
H
Output
Mail2 read (set
MBF2 HIGH)
TABLE 2 — PORT A ENABLE FUNCTION TABLE
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
PORT FUNCTION
H
X
High-Impedance
None
L
X
Input
None
LL
H
L
Input
None
LL
H
Input
Mail2 write
L
H
L
X
Output
None
LH
H
L
Output
FIFO read
L
H
L
H
X
Output
None
LH
H
Output
Mail1 read (set
MBF1 HIGH)
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