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| 型號： | IDT72T36125L5BBI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 20/57頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO 524X18 5NS 240BGA |
| 標準包裝： | 1 |
| 系列： | 72T |
| 功能： | 異步，同步 |
| 存儲容量： | 9.4K（524 x 18） |
| 數(shù)據(jù)速率： | 83MHz |
| 訪問時間： | 5ns |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BGA |
| 供應商設備封裝： | 240-PBGA（19x19） |
| 包裝： | 托盤 |
| 其它名稱： | 72T36125L5BBI |
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27
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
OUTPUTS:
FULL FLAG (
FF/IR )
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (
FF) function
is selected. When the FIFO is full,
FF will go LOW, inhibiting further write
operations. When
FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the
IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768
fortheIDT72T3695,65,536fortheIDT72T36105,131,072fortheIDT72T36115
and 262,144 for the IDT72T36125). See Figure 11, Write Cycle and Full Flag
Timing (IDT Standard Mode), for the relevant timing information.
In FWFT mode, the Input Ready (
IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
anyfreespaceleft,
IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads
are performed after a reset (either
MRSorPRS),IRwillgoHIGHafterD writes
to the FIFO (D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097
for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685,
32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the
IDT72T36115 and 262,145 for the IDT72T36125). See Figure 14, Write
Timing (FWFT Mode), for the relevant timing information.
The
IRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IRisonegreaterthanneededto
assert
FF in IDT Standard mode.
FF/IRissynchronousandupdatedontherisingedgeofWCLK. FF/IRare
double register-buffered outputs.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
write pointer to the ‘marked’ location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
EMPTY FLAG (
EF/OR )
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF)
functionisselected. WhentheFIFOisempty,
EFwillgoLOW,inhibitingfurther
readoperations. When
EFisHIGH,theFIFOisnotempty.SeeFigure12,Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
therelevanttiminginformation.
InFWFTmode,theOutputReady(
OR)functionisselected.ORgoesLOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs.
ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
the last word from the FIFO memory to the outputs.
OR goes HIGH only with
a true read (RCLK with
REN = LOW). The previous data stays at the outputs,
indicatingthelastwordwasread. Furtherdatareadsareinhibiteduntil
ORgoes
LOW again. See Figure 15, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
OR isatripleregister-bufferedoutput.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF)
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAFwillgoLOWafter(D - m)wordsarewritten
to the FIFO. The
PAF willgoLOWafter(1,024-m)writesfortheIDT72T3645,
(2,048-m) writes for the IDT72T3655, (4,096-m) writes for the IDT72T3665,
(8,192-m) writes for the IDT72T3675, (16,384-m) writes for the IDT72T3685,
(32,768-m)writesfortheIDT72T3695,(65,536-m)writesfortheIDT72T36105,
(131,072-m) writes for the IDT72T36115 and (262,144-m) writes for the
IDT72T36125. The offset “m” is the full offset value. The default setting for this
value is stated in the footnote of Table 3.
In FWFT mode, the
PAF will go LOW after (1,025-m) writes for the
IDT72T3645, (2,049-m) writes for the IDT72T3655, (4,097-m) writes for the
IDT72T3665 and (8,193-m) writes for the IDT72T3675, (16,385-m) writes for
the IDT72T3685, (32,769-m) writes for the IDT72T3695, (65,537-m) writes for
the IDT72T36105, (131,073-m) writes for the IDT72T36115 and (262,145-m)
writes for the IDT72T36125, where m is the full offset value. The default setting
for this value is stated in Table 4.
See Figure 23, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
If asynchronous
PAF configurationisselected,thePAF isassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).
PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). Ifsynchronous
PAF
configuration is selected, the
PAFisupdatedontherisingedgeofWCLK. See
Figure 25, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Mode).
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
write pointer to the ‘marked’ location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE)
The Programmable Almost-Empty flag (
PAE)willgoLOWwhentheFIFO
reaches the almost-empty condition. In IDT Standard mode,
PAEwillgoLOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 24, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
If asynchronous
PAEconfigurationisselected,the PAEisassertedLOW
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). Ifsynchronous
PAE
configuration is selected, the
PAEisupdatedontherisingedgeofRCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode).
HALF-FULL FLAG (
HF )
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyondhalf-fullsets
HFLOW.TheflagremainsLOWuntilthedifferencebetween
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets
HF
HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(
MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 1,024 for the
IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192
for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the IDT72T3695,
65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for
the IDT72T36125.
In FWFT mode, if no reads are performed after reset (
MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 1,025 for the
IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for
the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for
the IDT72T36125.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because
HFisupdatedbybothRCLKand
WCLK, it is considered asynchronous.
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| IDT72T36125L6-7BB | 功能描述:IC FIFO 524X18 6-7NS 240BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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