參數(shù)資料
型號(hào): IDT72T36125L5BBI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 37/57頁
文件大?。?/td> 0K
描述: IC FIFO 524X18 5NS 240BGA
標(biāo)準(zhǔn)包裝: 1
系列: 72T
功能: 異步,同步
存儲(chǔ)容量: 9.4K(524 x 18)
數(shù)據(jù)速率: 83MHz
訪問時(shí)間: 5ns
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 240-BGA
供應(yīng)商設(shè)備封裝: 240-PBGA(19x19)
包裝: 托盤
其它名稱: 72T36125L5BBI
42
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FEBRUARY 4, 2009
Figure
16.
Read
Cycle
and
Read
Chip
Select
Timing
(First
Word
Fall
Through
Mode)
WCLK
12
WEN
D0
-
Dn
RCLK
REN
Q0
-
Qn
PAF
HF
PAE
IR
OR
W
1
W
2
W
3
W
m+2
W
[m+3]
tRCSHZ
tSKEW1
tENH
tDS
tDH
tA
tPAFS
tWFF
tENS
RCS
tSKEW2
W
D
5907
drw21
tPAES
W
[D-n]
W
[D-n-1]
tA
W
[D-1]
W
D
tA
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
tENS
1
tENS
tRCSLZ
tENS
tHF
tREF
D-1
]
[
W
D-1
]
[
W
tENH
NOTES:
1.
t
SKEW1
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
IR
will
go
LOW
after
one
WCLK
cycle
plus
t
WFF
.
If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
t
SKEW1
,then
the
IR
assertion
may
be
delayed
one
extra
WCLK
cycle.
2.
tSKEW2
is
the
minimum
time
between
a
rising
RCLK
edge
and
a
rising
WCLK
edge
to
guarantee
that
PAF
will
go
HIGH
after
one
WCLK
cycle
plus
t
PAFS
.
If
the
time
between
the
rising
edge
of
RCLK
and
the
rising
edge
of
WCLK
is
less
than
t
SKEW2
,then
the
PAF
deassertion
may
be
delayed
one
extra
WCLK
cycle.
3.
LD
=
HIGH.
4
.
n=
PAE
Offset,
m
=
PAF
offset
and
D
=
maximum
FIFO
depth.
5
.
D
=
1,025
for
IDT72T3645,
2,049
for
IDT72T3655,
4,097
for
IDT72T3665,
8,193
for
IDT72T3675,
16,385
for
IDT72T3685,
32,769
for
the
IDT72T3695,
65,537
for
the
IDT72T36105,
131,073
for
the
IDT72T36115
and
262,145
for
the
IDT72T36125.
6.
OE
=
LOW.
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